# New blog -> sdr-prototypes

I made a separate blog for SDR-prototypes:

https://sdr-prototypes.blogspot.com/

The first post describes a HF only version of BBRF103 with fixed xtal oscillator reference named HF103.

Thanks to All!

Ciao

Oscar

# PScope a useful tool

To refine and measure the hardware and software performance of SDRs similar to BBRF103 there is an excellent software tool developed at the time by Linear Technology, today Analog Devices.

PScope allows you to quickly evaluate the performance of ADC chips.

I recommend the web page PScope: High-Speed ADC Data Collection Software on the Analog site where there is also a link to download installation file http://ltspice.analog.com/software/ltcps.exe it is free.

The video is also on youtube

The application has a help file and Analog Devices presents a PScope-Basics  page.

When used with ADC development boards the program requires specific drivers but can be installed without any driver.
It is possible to input the data we want to measure through a file that has a specific format that I tried to emulate by replicating the header of the file.
The files have the extension .adc
Our program, in my case ExtIO.dll will call my PScopeShot function specifying the name of the file that will be created, a title, a short description, the sample rate, the data pointer, their length.

I'm trying to figure out if the performance of my RF103 prototype (an HF-only version of BBRF103 with minor modifications) can be improved in hardware or software.

In the Extio.dll in the debugging configuration I have activated the possibility to replace the data generated by the ADC with a virtual buffer that contains the samples of a 16 bit sinusoid sampled and explored at the desired frequency.

In the initialization procedure of the dll I added the code:

…#ifndef _NO_PScope_ACTIVE_/* Virtual sine generator test PScope*/ unsigned int kidx = 0; float samplerate = adcfixedfreq; unsigned int mdf = Xfreq * ((double) 65386000.0/samplerate); // freq correction short* testdata = (short *) malloc(RF_TABLE_SIZE * sizeof( short)); // test buffer data unsigned int numsamples = global.transferSize/sizeof(short); for (unsigned int n =0; n < numsamples; n++ ) {   kidx %= RF_TABLE_SIZE;   testdata[n] = sine_table_16bit[kidx] ;   kidx += mdf; } PScopeShot("VirtualSineWave.adc", "RF103_7a", "VirtualSineWave.adc input virtual test 16 bit sine", testdata, samplerate, numsamples ); free (testdata);#endif // _PScope_ACTIVE_...

The PscopeShot procedure is defined as

int PScopeShot(const char * filename, const char * title2, const char * title1, short * data, float samplerate, unsigned int numsamples ){ FILE *fp; fp = fopen(filename, "w+"); fputs("Version,115\n", fp); fprintf(fp, "Retainers,0,1,%d,1024,0,%f,1,1\n",numsamples,samplerate ); fputs("Placement,44,0,1,-1,-1,-1,-1,88,40,1116,879", fp); fputs("WindMgr,7,2,0\n", fp); fputs("Page,0,2\n", fp); fputs("Col,3,1\n", fp); fputs("Row,2,1\n", fp); fputs("Row,3,146\n", fp); fputs("Row,1,319\n", fp); fputs("Col,2,1063\n", fp); fputs("Row,4,1\n", fp); fputs("Row,0,319\n", fp); fputs("Page,1,2\n", fp); fputs("Col,1,1\n", fp); fputs("Row,1,1\n", fp); fputs("Col,2,425\n", fp); fputs("Row,4,1\n", fp); fputs("Row,0,319\n", fp); fprintf(fp,"DemoID,%s,%s,0\n", title1, title2 ); fprintf(fp,"RawData,1,%d,16,-32768,32767,%f,-3.276800e+04,3.276800e+04\n", numsamples,samplerate); for (unsigned int n = 0; n < numsamples; n++ )  {    fprintf(fp, "%d\n", data[n]);  } fputs("end\n", fp); return fclose(fp);}

The acquired file of the virtual generator signal when loaded in PScope File menu draws:

No bad for a 16bit software table lookup implementation!

Here the picture of the HDSDR output when we select the RF virtual tone generator. It’s very similar to PScope analysis and result.

In a second test I forced the software DDC input samples to a constant value, a DC component.

… short anyvalue = 0x5aC3; for (unsigned int n =0; n < numsamples; n++ ) { testdata[n] = anyvalue; } PScopeShot("VirtualDClevel.adc", "RF103_7a", "VirtualDClevel.adc input virtual test DC value", testdata, samplerate, numsamples );…

The PScope analysis shows no noise component as we have a perfect stable input virtual level.

SNR not available as there as noise is absent.

In the HDSDR world we get:

This only verifies that there are no noise components added by the DDC.

## BBRF103  posts

Some variations of ExtIO_sddc.dll architecture        31 August, 2017

Troubleshooting BBR103          22 September, 2017

BBRF103 and ExtIO.dll ver. 0.96 get 32 MHz span    1 March, 2018

R820T2 update - BBRF103_2 PCB           10 April, 2018

BBRF103 - Band L reception                   26 May, 2018

Just another BBRF103 version                14 August, 2018

BBRF103-2 RC3 is here!                         1 September, 2018

BBRF103 Construction notes                   4 May, 2019

BBRF103 Some measurements               20 May, 2019

Receivers similar to BBRF103 ?               08 June, 2020

PScope a useful tool                              19 June, 2020

# Receivers similar to BBRF103 ?

Some receivers with an architecture similar to BBRF103 appeared in the web during this look down time.
I tried to contact the authors not for copyright issues, being BBRF103 completely open source but to exchange some experiences. A contacted person wrote me that the project is new and fully original, but I think I reached the re-seller and not the designer.
So I signal my interest in talking with the real authors of the devices.
I list the devices with links to images that are in these weeks at the following links.

If someone has a review or any other info please send it to me.

Thanks, everyone,  ik1xpv AT gmail DOT com

Update 15 August, 2020

- If you want to give a try to BBRF103 software with these receivers, here the compiled ExtIO_sddc.dll : v.0.96 (HF only) and v.0.98 (HF and VHF).

Update 19 August, 2020

- The RX888 SDR – Up Close Photos at  https://swling.com/blog/2020/08/the-rx888-sdr-up-close-photos/

- The RX-888 Team sent me the link to they RX-888 software at

source:

# RX-666 ?

source:

https://img.alicdn.com/imgextra/i2/22088642/O1CN01wrOfUF2Di5PDC8KRa_!!22088642.jpg

https://img.alicdn.com/imgextra/i4/22088642/O1CN017bLC3v2Di5OpbZuEj_!!22088642.jpg

https://img.alicdn.com/imgextra/i3/22088642/O1CN01B86EWy2Di5P6pKtn4_!!22088642.jpg

https://img.alicdn.com/imgextra/i3/22088642/O1CN01hqZ7N92Di5OrG2ydq_!!22088642.jpg

## BBRF103  posts

Some variations of ExtIO_sddc.dll architecture        31 August, 2017

Troubleshooting BBR103          22 September, 2017

BBRF103 and ExtIO.dll ver. 0.96 get 32 MHz span    1 March, 2018

R820T2 update - BBRF103_2 PCB           10 April, 2018

BBRF103 - Band L reception                  26 May, 2018

Just another BBRF103 version                  14 August, 2018

BBRF103-2 RC3 is here!                         1 September, 2018

BBRF103 Construction notes                   4 May, 2019

BBRF103 Some measurements               20 May, 2019

Receivers similar to BBRF103 ?               08 June, 2020

PScope a useful tool               19 June, 2020

# BBRF103 Some measurements

In the construction of BBRF103 the evaluation kit of Cypress for the FX3 is used as it is and the ADC printed circuit board is realized with 2 layers as a compromise to reduce the cost of realization.

I try to evaluate now with homemade measurements how close the performance is and how good it is.

"(pag 1) ...The LTC2217 includes 81.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR)

(pag 24) … Digital Output Randomizer
Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling, or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude.
The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output Randomizer function is active when the RAND pin is high.

(pag 25)... Internal Dither
The LTC2217 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels.
As shown in Figure 15, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in typically less than 0.5dB elevation in the noise floor of the ADC as compared to the noise floor with dither off, when a suitable input termination is provided (see Demo Board schematic DC996B).

".

I made a sinusoidal generator using an old 10MHz TCXO followed by a ladder quartz filter made with cheap 10MHz quartz.

I calibrated the TCXO at 9.9981 MHz to pass through the quartz filter.
Before the filter, an SBF5089Z amplifier allows to obtain after the filter a level of +2dBm on 50 Ohm.
Finally, a series of resistive attenuators allows you to adjust the output level.
The aim is to obtain a generator with good dynamics and low noise. The result has 2nd and 3rd harmonic level at -50dB.

Here are a few measures

BBRF103 HF antenna is connected to the attenuator output.
BBRF103 control panel allows to activate dither and randomize.

Hereafter the level is -1dBFS, DITH and RAND are active.

Hereafter the same -1dBFS level, DITH and RAND are OFF

With strong and stationary signals the interference of the data bus is evident and the use of dither and randomize is effective.
Referring to the ADC datasheet with reference to these approximate measurements, it seems to me that the current layout of the 2-layer PCB and the adc databus, which also continues in the evaluation PCB of the FX3, worsen the spurious performance by 10-15 dB compared to the optimal layout of the PCB.

It would be possible to realize a single multilayer PCB including FX3 and ADC with better performances following the datasheet's layout indications.

# BBRF103 Construction notes

These days I assembled a second prototype of BBRF103 receiver.  Here are some notes.

### Power supply

I made a different power harness. The purpose is to allow the circuit to be powered by the USB cable with VBUS or via a separate 5Volt power connector.

So far in the diagrams of BBRF103 the input of the 5V power supply to the PCB is taken from the VBUS of CYUSB3KIT-003.

I noticed on my two prototypes some problem related to the intervention of the protection circuit (U11 sheet 2 of 8, CYUSB3KIT scheme) on the Cypress plate and caused by the current increase required in some phases of power-up of the PCB BBRF103 and R820T2 use.

I modified the input of the 5Volt and connected it upstream of the protection circuit using the J3 jumper as a connector.

The scheme is as follows:

The current consumption of complete BBRF103 using Tuner R820T2 is about 530mA at 5Vdc.

From left to right

- 5Volt dc external input (optional)

- latched pushbutton VBUS / extenal 5V

- USB3 connector

- ON / OFF

### Shielding box

The box used is made of aluminum, it has dimensions 100x76x35mm, currently at Banggood it is available only in a golden color. The surface is brushed and treated with an insulating process so it is necessary to sandpaper the contact surfaces to obtain an electrical contact when it closes.

In the grooves on the long sides I inserted after scratching the rail a strip of Desoldering Copper Wick as a contact gasket.

### Heat dissipation

The ADC LTC2217 and the tuner R820T dissipate more than one Watt in heat. To keep the temperature of the chips lower, I tried two passive aluminium heat sinks that lead the heat to the aluminium box, which acts as a heat sink, reducing the temperature of the chips by 20-30° C.

The radiators are fixed with some M2 nylon insulating screws and nuts. I used a slightly modified PCB from BBRF103-2 layout.

### Stand alone static current test

Assembling the pcb I have tried a simple method to verify errors of power supply rails.

Each block of the circuit is powered separately through a filter inductor. So not mounting these components it is easy to measure the current absorbed by various blocks on the PCB BBRF103-2 before connecting the CYUSB3KIT-003 board.

Here is a table with the measured power consumption of three blocks in a static way.
I have not mounted FL1, FL2, FL3.
I connected a 5Volt /500mA power supply to the LDO power supply of the plate and
I measured the current at the unassembled inductors by injecting an external voltage, getting:

 Block Current Measuring point Oscillator SI5351 15-16 mA FL3 / external power supply 3.3V Tuner R820T2 80-85 mA FL2 / external power supply 3.3V ADC LTC2217 269-210 mA FL1 / external power supply 5V (ADC gets 3.3V via LDO)

In case, inspect the component mounting and check the welds with a microscope or lens.

# BBRF103-2 RC3 is here!

Radek Haša is a shortwave and airband listener living in Czech republic.
He decided to redesign the PCB layout and assembled a prototype of the BBRF103-2.
Thanks for allowing his project to be published.

While designing the PCB in Eagle 8.x format, he noticed and fixed some bugs in my layout.

- Referring to transformers T1,T2,T3. The Coilcraft WBC4-6TL type is better than the WBC4-1TL. The insertion loss is 0.65 dB instead of 1 dB. (WBC datasheet)
Note that terminals 4 and 6 of the primary winding are interchanged in the electric scheme and the SMD footprint used in the PCB. This does not affect performance and will be corrected in the future PCB version to match the original SMD footprint.

- The Q1,Q2,Q3,Q4 SMD footprint is corrected in RC3 PCB.

- C44 and C55 silkscreen locations are swapped in the BBRF103-2 original PCB. Footprint is corrected in RC3 PCB layout.

Prototype was tested on desktop PC equipped with Intel Pentium G4600 CPU and B150 chipset USB 3.0 hub controller. Hereafter some pictures of prototype under testing.

He made some test of temperature of the ADC and R820T2 in VHF mode.
“There are no heatsinks on ADC and R820T2. The temperature of the ADC reached 73 ° C while the R820T2 reached 60 ° C at 100MHz. Room temperature was 27 ° C.“

WARNING: notice that this description is a BETA test version without any warranty and is intended for non-commercial purposes.

The archive contains:
BBRF103-RC3.sch
BBRF103-RC3.brd
BBRF103.ods