ik1xpv hamradio software & hardware

BBRF103 Some measurements

In the construction of BBRF103 the evaluation kit of Cypress for the FX3 is used as it is and the ADC printed circuit board is realized with 2 layers as a compromise to reduce the cost of realization.

I try to evaluate now with homemade measurements how close the performance is and how good it is.

Let's start with a few readings from the technical data sheet of the LTC2217 (https://www.analog.com/media/en/technical-documentation/data-sheets/2217f.pdf )

"(pag 1) ...The LTC2217 includes 81.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR)

(pag 24) … Digital Output Randomizer
Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling, or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude.
The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output Randomizer function is active when the RAND pin is high.


(pag 25)... Internal Dither
The LTC2217 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels.
As shown in Figure 15, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in typically less than 0.5dB elevation in the noise floor of the ADC as compared to the noise floor with dither off, when a suitable input termination is provided (see Demo Board schematic DC996B).



I made a sinusoidal generator using an old 10MHz TCXO followed by a ladder quartz filter made with cheap 10MHz quartz.

I calibrated the TCXO at 9.9981 MHz to pass through the quartz filter.
Before the filter, an SBF5089Z amplifier allows to obtain after the filter a level of +2dBm on 50 Ohm.
Finally, a series of resistive attenuators allows you to adjust the output level.
The aim is to obtain a generator with good dynamics and low noise. The result has 2nd and 3rd harmonic level at -50dB.

Here are a few measures

BBRF103 HF antenna is connected to the attenuator output.
BBRF103 control panel allows to activate dither and randomize.


Hereafter the level is -1dBFS, DITH and RAND are active.


High resolution image link


Hereafter the same -1dBFS level, DITH and RAND are OFF


High resolution image link

With strong and stationary signals the interference of the data bus is evident and the use of dither and randomize is effective.
Referring to the ADC datasheet with reference to these approximate measurements, it seems to me that the current layout of the 2-layer PCB and the adc databus, which also continues in the evaluation PCB of the FX3, worsen the spurious performance by 10-15 dB compared to the optimal layout of the PCB.

It would be possible to realize a single multilayer PCB including FX3 and ADC with better performances following the datasheet's layout indications.


BBRF103 Construction notes

These days I assembled a second prototype of BBRF103 receiver.  Here are some notes. 

Power supply

I made a different power harness. The purpose is to allow the circuit to be powered by the USB cable with VBUS or via a separate 5Volt power connector.

So far in the diagrams of BBRF103 the input of the 5V power supply to the PCB is taken from the VBUS of CYUSB3KIT-003.

I noticed on my two prototypes some problem related to the intervention of the protection circuit (U11 sheet 2 of 8, CYUSB3KIT scheme) on the Cypress plate and caused by the current increase required in some phases of power-up of the PCB BBRF103 and R820T2 use.

I modified the input of the 5Volt and connected it upstream of the protection circuit using the J3 jumper as a connector.

The scheme is as follows:



The current consumption of complete BBRF103 using Tuner R820T2 is about 530mA at 5Vdc.


From left to right

- 5Volt dc external input (optional)

- latched pushbutton VBUS / extenal 5V

- USB3 connector

- ON / OFF


Shielding box

The box used is made of aluminum, it has dimensions 100x76x35mm, currently at Banggood it is available only in a golden color. The surface is brushed and treated with an insulating process so it is necessary to sandpaper the contact surfaces to obtain an electrical contact when it closes.

In the grooves on the long sides I inserted after scratching the rail a strip of Desoldering Copper Wick as a contact gasket.


Heat dissipation

The ADC LTC2217 and the tuner R820T dissipate more than one Watt in heat. To keep the temperature of the chips lower, I tried two passive aluminium heat sinks that lead the heat to the aluminium box, which acts as a heat sink, reducing the temperature of the chips by 20-30° C.




The radiators are fixed with some M2 nylon insulating screws and nuts. I used a slightly modified PCB from BBRF103-2 layout.

Stand alone static current test

Assembling the pcb I have tried a simple method to verify errors of power supply rails.

Each block of the circuit is powered separately through a filter inductor. So not mounting these components it is easy to measure the current absorbed by various blocks on the PCB BBRF103-2 before connecting the CYUSB3KIT-003 board.

Here is a table with the measured power consumption of three blocks in a static way.
I have not mounted FL1, FL2, FL3.
I connected a 5Volt /500mA power supply to the LDO power supply of the plate and
I measured the current at the unassembled inductors by injecting an external voltage, getting:

Block Current Measuring point
Oscillator SI5351 15-16 mA FL3 / external power supply 3.3V
Tuner R820T2 80-85 mA FL2 / external power supply 3.3V
ADC LTC2217 269-210 mA FL1 / external power supply 5V (ADC gets 3.3V via LDO)

In case, inspect the component mounting and check the welds with a microscope or lens.


BBRF103-2 RC3 is here!

Radek Haša is a shortwave and airband listener living in Czech republic.
He decided to redesign the PCB layout and assembled a prototype of the BBRF103-2.
Thanks for allowing his project to be published.


While designing the PCB in Eagle 8.x format, he noticed and fixed some bugs in my layout.

- Referring to transformers T1,T2,T3. The Coilcraft WBC4-6TL type is better than the WBC4-1TL. The insertion loss is 0.65 dB instead of 1 dB. (WBC datasheet)
Note that terminals 4 and 6 of the primary winding are interchanged in the electric scheme and the SMD footprint used in the PCB. This does not affect performance and will be corrected in the future PCB version to match the original SMD footprint.

- The Q1,Q2,Q3,Q4 SMD footprint is corrected in RC3 PCB.

- C44 and C55 silkscreen locations are swapped in the BBRF103-2 original PCB. Footprint is corrected in RC3 PCB layout.

Prototype was tested on desktop PC equipped with Intel Pentium G4600 CPU and B150 chipset USB 3.0 hub controller. Hereafter some pictures of prototype under testing.





He made some test of temperature of the ADC and R820T2 in VHF mode.
“There are no heatsinks on ADC and R820T2. The temperature of the ADC reached 73 ° C while the R820T2 reached 60 ° C at 100MHz. Room temperature was 27 ° C.“

WARNING: notice that this description is a BETA test version without any warranty and is intended for non-commercial purposes.

Radek’s PCB design files can be downloaded here: http://www.steila.com/radek/BBRF103_2_RC3.zip
The archive contains:

Finally please notice that ExtIOsddc.dll ver 0.96 software does not yet control the antenna power via dll panel window and to enable VHF (R820T2) mode you must undefine _NO_TUNER_ in config.h and recompile.



email: ik1xpv AT gmail DOT com

Just another BBRF103 version

A new board to experiment with undersampling technique.

“..If we use the sampling frequency less than twice the maximum frequency component in the signal, then it is called undersampling. Undersampling is also known as band pass sampling, harmonic sampling or super-Nyquist sampling. Nyquist-Shannon Sampling theorem, which is the modified version of the Nyquist sampling theorem, says that the sampling frequency needs to be twice the signal bandwidth and not twice the maximum frequency component, in order to be able to reconstruct the original signal perfectly from the sampled version. If B is the signal bandwidth, then Fs > 2B is required where Fs is sampling frequency. The signal bandwidth can be from DC to B or from f1 to f2 where B = f2 – f1. The aliasing effect due to the undersampling technique can be used for our advantage. When a signal is sampled at a rate less than twice its maximum frequency, the aliased signal appears at Fs – Fin, where Fs is the sampling frequency and Fin in the input signal frequency. “ from Why Use Oversampling when Undersampling Can do the Job? - Texas Instruments.

In an example case looking at FM band we sample the input 98 MHz with Fs = 56MHz and the aliased component will appear at 14 MHz ( 56*2 – 98).
As we know in advance that the signal is aliased, we can recover the actual frequency by using the N*Fs – Fin relationship. The undersampling technique allows the ADC to behave like a mixer or a down converter in the receive chain. For a band-limited signal of 98 MHz with a 20-MHz signal bandwidth, the sampling rate (Fs) of 56 Msps, the aliased component referred to 2*Fs will appear between 4MHz to 24 MHz (20 ±10 MHz.
An analog band pass filter is required at ADC input to avoid interference from other Nyquist band.


Undersampling Case of 98MHz Signal with 20MHz Bandwidth.


I designed a new breadboard with some modification. The PCB is named BBRF103 ver 0.5.


BBRF103 ver 0.5 - block diagram.

The J1 input uses a band stop filter for the FM Band 88-108 MHz.
This input is planned for experimental use within 120-500 MHz frequency range. Some specific band pass filter and LNA will be externally added for 50MHz, 144MHz or 432MHz band.


The FM Band Stop Filter - LTspice simulation.

The J2 input has a band pass filter for the FM band to analyze the full 88-108 MHz band spectrum at once. This filter is quite simpler as the FM signals are very strong versus possible interference.


FM band filter response.

Finally J3 is the HF input. The filter components values are changed from first version of BBRF103.


HF low pass filter.

The connector J4 is an optional input for an external reference signal. A capacitor must be mounted to enable this signal.

J5 and J6 are two programmable clock output from the Si5351 generator. May be used to synchronize external tuner oscillator.

RF switch type
I like to test a bi-stable subminiature DIP relay type HFD2/005-M-L2-D to switch RF instead of active switches. 
The relay is a 5Volt dual coil latched one.  I shielded it using adhesive copper tape that will be soldered to the PCB ground plane.


Relays used. The left one with a copper tape shield added.

The board scheme and PCB layout is at link http://www.steila.com/test/BBRF103_5.pdf

24/04/2019 - here http://www.steila.com/test/BBRF103_5B.pdf annotated scheme circuit to keep relays off during power on.

I preview to receive the PCB within September and then to start testing.


24/04/2019 - My prototype shows that the PCB layout around the PCB is worse and noisier than the previous PCBs. A makeover is needed.


email: ik1xpv AT gmail DOT com




BBRF103 - Band L reception

BBRF103_2 PCB adds a switchable LNA power supply through the antenna cable

I tested it with an Outernet L-band ceramic patch antenna.  This antenna requires  power and can be connected to BBRF103_2 PCB. The antenna onboard filter helps to reduce problems from interfering signals and restricts reception to 1525 - 1559 MHz.

The antenna is a 12 by 12 cm square PCB.  I placed it into a plastic radome ( an empty IKEA FIXA series DIY kit ).



A picture of the installed radome.


Some screenshots of the band L:


Reception of Inmarsat C  with  WinSTD-C program.



Ten MHz down there are many other satellite signals.  The gap in the spectrogram shows the BBRF103 noise when the antenna power is switched off;  two spurious signals are visible on the right.

BBRF103_2 PCB notes

ADC:  I mounted the BBRF103_2 prototype with a LTC2208 ADC instead of LTC2217. I wanted to check compatibility and I had not any other LTC2217 sample. The LTC2208 is a little noiser than LTC2217 by some 2 dB.  The LTC2208 draws  some mA more current.

Antenna power: The  scheme uses 2N3906,2N3904 : Q2,Q3,Q4,Q5. The pcb footprint is wrong. Mount them upside down on the pc board.

I mounted R42,R43,R44 = 10 Ohm,  it increases the output current. 

R820T2:  I added some bypass capacitors to the VCT line on the top layer. 

Temperature: I made some measure of the temperature of R820T2 and LTC2208 with a small copper radiator.


The temperature of the ADC with a small copper radiator reaches 67 ° C while the R820T2 with the radiator reaches 45 ° C.

Preview: I will use MAX4995 50mA to 600mA Programmable Current-Limit Switch to control the LNA current in a new pcb's revision and some heat radiators will be added to ADC and RT820T2...


 email: ik1xpv AT gmail DOT com

R820T2 update - BBRF103_2 PCB

A bug crashed the USB3.0 stream at random time while the R820T2 tuner was active. ( Troubleshooting BBR103 )

It was caused by a spurious coupling via the 3V3 power supply. 

I thought of a problem in the firmware of FX3 while the cause was hardware.
I decoupled the R820T2 3V3 power supply using a separate LDO from the 5V USB bus to
solve the problem in the prototype.

The R820T can be used to receive frequency band in the range 30MHz -1800MHz.
The tuner uses a clock generated by Si5351A at 32.000MHz, the REGDIV bit of reg 4 is set to 1 to divide it by two internally to the nominal 16MHz.
The IF output is selected at 5MHz ( I used up to 7.5MHz) and it’s sampled by the ADC at 64Msps and then decimated down to 8Msps or less. The R820T data sheet states that the standard IF filters are implemented for 6/7/8 MHz channel bandwidths.

The LNA, the mixer and the VGA gains can be set manually although their precise values are absent from the datasheet.
They can also be set automatically via automatic gain control (AGC) in order to optimize the signal to noise ratio (SNR).

A revision of PCB  BBRF103_2 has been designed: ( www.steila.com/test/BBRF103_2B.pdf )

- A separate LDO voltage regulator for R820T2 has been added

- 1000 uF capacitors with a mosfet delayed switch has been added to 5VBUS and 3V3 R820T2.

- Antenna power supply with software switch added to HF and VHF input

- SMD pad dimensions have been increased a little bit to simplify manual assembly.

- Board profile modified to house SMA connectors. 

- BAV99 smd layout corrected.

- A header P7 with some GPIOs added.

- Possibility of external frequency reference input to Si5351a  ( P8 ).

- Aux clock ouput  (P9).


I just received the manufactured pcb and possibly I will test it in the next month.



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