# 3radio project - Part 4

Here some test results to evaluate the hardware performance and the use of a pseudo random binary sequence as reference to cross correlate the streams received from the 3radio, a radio composed by  multiple RTL-SDR hardware.

The 3radio has been tuned to 69 MHz center frequency and a sampling rate of 2048000 Hz has been chosen.  3 streams of 100000 IQ sample have been recorded using librtlsdr . The real time length is half a second.

The reference signal was a pseudo noise digital stream at 2 MHz shift rate.

The same signal was routed via separated switching diodes to all the RTL-SDR receivers.

Sequences of  about 3 ms or 6000 bits have been generated. A delay of some hundred of ms separates the different bursts. The reason was to be able to recognize some sync reference just looking to signals in time.

The previous figure shows the IQ streams in time, a chunk of about 6200 samples at 2048000 sampling is selected.

A script in python was written to compute the cross correlation. Here after the script:

# ik1xpv oscar steila 2016
# complex cross correlation of N files with 8 bit rawIQ data (RTL-SDR)

import math
import cmath
import matplotlib.pyplot as plt
import numpy as np
from scipy import signal

signals = [] #array of processed signals

# data raw IQ files [howmany required]
rawfiles = ["testX1", "testX2", "testX3"]

# The raw, captured IQ data is 8 bit unsigned data.
# Each I and Q value varies from 0 to 255.
# To get from the unsigned (0 to 255) range we need to subtract 127.5
# from each I and Q value, which results in a new range from -127.5 to +127.5.
# The complex data is y = I + jQ and we subtract 127.5 +127.5j

for filename in rawfiles:
y = np.fromfile(filename, dtype=np.dtype("u1"))
y = y.astype(np.float32).view(np.complex64)
y -= (127.5 + 127.5j)
signals.append(y)

ncorr = len(signals)
chunk_length = len(signals[0])
print(str(ncorr) + " sample vectors of " +str( chunk_length) +" samples length" )
print("filenames:",rawfiles)
for i in range(ncorr):
sig1 = signals[i]
ix = i+1
if ix == ncorr:
ix = 0
sig2 = signals[ix]
print("cross correlation",i,"<->",ix)
ccorr = signal.fftconvolve(sig1, np.conj(sig2[::-1]))
mod = np.linalg.norm(sig1)*np.linalg.norm(sig2[::-1])
print("mod", mod)
print("ccorr lenth", len(ccorr))
peakat = np.argmax(np.abs(ccorr))
print ("max position:", peakat)
print ("ccorr peak value:", cmath.polar(ccorr[peakat]))
print ("normalized value:", cmath.polar(ccorr[peakat])/mod,"\n" )
zcorr = ccorr[peakat - 500: peakat + 500]/mod
ss = "Correlation "+str(i)+"-"+str(ix)
plt.figure("CROSS CORRELATION")
plt.subplot(3,1,1+i)
plt.text(60000,2*1e7,ss)
plt.plot(np.abs(ccorr))

plt.figure("normalized zoom near maximum")
plt.subplot(3,1,1+i)
plt.xlabel('note: signals are aligned with the max in position 500')
plt.text(20,0.1,ss)
plt.plot(np.abs(zcorr))

plt.show()

The cross correlation was computed over the whole streams length of 1000000 samples.

I got the following results and plots:

========= RESTART: C:\Users\Oscar\Documents\Python_code\Correla1.py =========
3 sample vectors of 1000000 samples length
filenames: ['testX1', 'testX2', 'testX3']
cross correlation 0 <-> 1
mod 1.43562e+08
ccorr lenth 1999999
max position: 1003874
ccorr peak value: (87426948.37116447, -3.0573868558433284)
normalized value: [ 6.08982555e-01 -2.12965829e-08]

cross correlation 1 <-> 2
mod 1.71879e+08
ccorr lenth 1999999
max position: 1002975
ccorr peak value: (124230240.98693986, 1.4627621167409313)
normalized value: [ 7.22777073e-01 8.51041512e-09]

cross correlation 2 <-> 0
mod 1.92693e+08
ccorr lenth 1999999
max position: 993148
ccorr peak value: (131838258.19245286, 1.598828000018114)
normalized value: [ 6.84189098e-01 8.29729322e-09] .

The results look quite good nevertheless the reference signal was far from perfect as you can notice from the cross correlation side lobes.

The time differences of the max positions define the time skewing between the streams. This time depends on the USB latency, on the different starting time of the software application trigger. I hope that the hardware clock skewing is solved with the synchronization.

# 3radio project - Part 3

The programmable 2-PLL VCXO clock synthesizer  CDCE925 from TI is configured to generate 12 MHz and 16 MHz clocks synchronous to the 28.8 MHz clock reference.

The 3radio prototype has been modified following the scheme:

TI ClockPro(TM) application is used to made the configuration file of CDCE925 while an I2C programmer (an Arduino board) is required to program it.

Other than the 12 MHz and 16 MHz clocks used for the HUB FE1.1s IC and the AT90USB162 uP a 10 MHz synchronous clock is generated for comparison to lab frequency standard.

The 28.8 MHz buffered output goes to a two xtal filter made with the 28.8 MHz xtals de-soldered from the RTL-SDR. This filter is used to obtain the sinusoidal output signal that synchronizes the RTL-SDR dongles.

The FFT analysis shows a 40 dB attenuation of high harmonics.

The CDCE925 has been mounted with dead-bug style and the cable used for the rtl-sdr 28.8MHz is RG174.  The cables have the same length, while for 12 MHz and 16 MHz a twisted wire pair has been used.

The 28.8 MHz TCXO and the 28.8 MHz xtal filter are on the top while the cdce925 is on the bottom side of the PCB. The black cables feed the clock to the RTL-SDR dongles. The grey twin wires on the left are the 12 and 16 MHz clocks.

# 3radio project - Part 2

Some tests have been made using the prototype described in 3radio project - Part 1.

The software uses rtl-sdr library.  It  runs 3 instances using synchronous transfer.    Each stream is recorded in a file as raw bytes.     A first graphical analysis and comparison is made using Audacity application.

The application programs all the units to the same frequency.   The central frequency is 60.0 MHz because the energy of Pseudo Random Noise Generator (PRNG) sequence is higher at low frequency.  The 3radio PRNG prototype has not jet a pulse sharpening circuit.

The PRNG has been programmed to generate at pseudo-random time intervals a sequence of 64 bits at 1Mbps with a good auto-correlation peak. Nevertheless the first measure has been made without any correlation processing, just looking at signal in time with Audacity app.

The picture shows the records made with a sampling rate of 2048 ksps and the gain set to 10dB. All the units are feed by the same PRNG signal. The signals are down-converted and recorded as complex base-band signal I&Q, here shown as stereo audio signals. The time scale is in 10 ms units as Audacity does not accept 2048 kHz sampling and 20.48 kHz is selected instead. The time span is about 500 ms.

The 3 streams are correlated and shown different latency time. I think latency is due to the different recording starting time and serialization over the USB link other than the pll phasing of RTL2832 and R820T.

Lucky the sampling synchronization is kept constant during the measure. So an head synchronization could be maintained for a long time.

Manually phasing the signals and zooming into the 64 bit sequence shows the strong correlation in between the 3 I&Q streams.

A phase rotation in the signals is expected as the PRNG signal is generated by a microprocessor running at 16.0 MHz with a xtal not synchronous to the 28.8MHz clock.

Note: an hardware improvement could be made synchronizing the 16.0 MHz clock of PRNG and the 12.0 MHz clock of HUB with the advantage of decreasing the eterodine signals.

# 3radio project - Part 1

The use of multiple RTL-SDR dongles as coherent receiver has been proposed since 2013.
In http://kaira.sgo.fi/2013/09/16-dual-channel-coherent-digital.html Juha Vierinen posted a two units hack.
Many others can be found Googling “rtl-sdr coherent receiver”

The first goal is a setup for coherence measure without sophisticate instruments.

Block diagram rev 1.0

It is a compact device that uses a single USB cable to acquire 3 SDR sample streams.

Thermal cooling is important to reach reliable performance.

The unit is housed into an aluminum box with the rtl-sdr screwed to the box wall.

Temperature range from 25°C to 85°C

The original MCX connector, the IR receiver and the led have been removed. Please keep the solder dots as flat as possible on the solder side.

Solder side

The rtl-sdr PCB has a 2.0 mm hole that can be used to fix the unit near the led position. A second 2.0 mm diameter hole is drilled in the position indicated in the picture.
Two 2.0 mm screws will rest the board against the aluminum wall. An electrical insulated thermal pad is placed in between the board and the aluminum.
90° SMA Female connectors has been used in the prototype.

Preliminary test wiring with a xtal oscillator feeding the other units.

As the TCXO 28.8MHz is not jet arrived in the mail, one of the original xtal oscillators has been used to drive the other two ones using a 14 pF capacitors (2*6.8pF in parallel).

The USB connectors has been replaced by wires to place the boards against the aluminum near the HUB PCB.

The red wire that goes to the antenna diode is carrying the pseudo random noise PRNG signal to the antenna inputs via a BAV99 diode gate.

The HUB  is a FE1.1s chip while the PRNG is a AT90USB162 wired to the 4th port of the HUB.

The plan is to use the PRNG sequence to synchronize the received streams during an initial calibration phase or every time the USB samples streams are stopped.

At the beginning the generator stream is used to measure some coherence figure...

early prototype

# ExtIO_H101.dll

Following the advice of Claudio Re I1RFQ and Ivan Guerini IW2KBK I spent some time in developing an ExtIO_H101.dll.

This dll follows the Alberto di Bene Winrad specifications for the external I/O DLL.

It allows the use of the H101 SDR receiver with many of the SDR applications that implement the ExtIO standard,

The last version is: ver 0.13

Here you can download the ExtIO_H101_013.zip  The archive contains the ExtIO_H101.dll ver 0.13

The MD5 hash file signature is c9eaf93506e31afbc1f2d7c3284d2897

It operates with OS in Italian or English

While ExtIO_H101_012.zip runs on English PC.   The archive contains the ExtIO_H101.dll ver 0.12

The MD5 hash file signature is dfb4a46321dc8380191b6ee98f1c3db3

Copy Extio_H101.dll file into the SDR application directory and then select the ExtIO_H101 from the SDR application setup.

The source code is at www.github.com/ik1xpv/ExtIO_H101

The dll is under development and it is not fully tested, you will use it at your own risk.

It has been tested in Windows 10, 8, 7 OS with HDSDR, SDRsharper.

Have you fun!

Here after some pictures from Ivan:

# The RTL2832+R820T RF GENERATOR hack 1.0

The hack 0.9 describes how to modify a RTL2832U+R820T dongle as RF generator.

I connected the generator to two RTL2832U+R820T receivers and I assumed the generator to be in the 0.5-1.5GHz range as indicated by the receivers screens.

That is not correct because the RTL_SDR receiver is sensitive to even harmonics of the tuning frequency.

The generator output is in the VCO range 1.770 - 3.54 GHz.

The error became evident when I connected the generator to a R&S FSV spectrum analyzer and got the following measures:

Spectrum analyzer settings: Center Frequency 1.8 GHz ; Span 3.6 GHz, Att 10dB.

Generator SDR# tune: 1GHz,

output spectrum: 2.0GHz (2x)

Generator SDR# tune: 0.9GHz,

output spectrum: 1.8GHz (2x)

Generator SDR# tune: 1.4 GHz,

output spectrum: 2.8GHz (2x)

When the generator is tuned to lower frequency the VCO is tuned to higher harmonics (power of 2).

Generator SDR# tune: 0.5 GHz,

output spectrum: 2.0 GHz ( 4x)

The generated signal is weak while clean.

The RTL2832+R820T RF GENERATOR hack 0.9

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