ik1xpv hamradio software & hardware

Just another BBRF103 version

A new board to experiment with undersampling technique.

“..If we use the sampling frequency less than twice the maximum frequency component in the signal, then it is called undersampling. Undersampling is also known as band pass sampling, harmonic sampling or super-Nyquist sampling. Nyquist-Shannon Sampling theorem, which is the modified version of the Nyquist sampling theorem, says that the sampling frequency needs to be twice the signal bandwidth and not twice the maximum frequency component, in order to be able to reconstruct the original signal perfectly from the sampled version. If B is the signal bandwidth, then Fs > 2B is required where Fs is sampling frequency. The signal bandwidth can be from DC to B or from f1 to f2 where B = f2 – f1. The aliasing effect due to the undersampling technique can be used for our advantage. When a signal is sampled at a rate less than twice its maximum frequency, the aliased signal appears at Fs – Fin, where Fs is the sampling frequency and Fin in the input signal frequency. “ from Why Use Oversampling when Undersampling Can do the Job? - Texas Instruments.

In an example case looking at FM band we sample the input 98 MHz with Fs = 56MHz and the aliased component will appear at 14 MHz ( 56*2 – 98).
As we know in advance that the signal is aliased, we can recover the actual frequency by using the N*Fs – Fin relationship. The undersampling technique allows the ADC to behave like a mixer or a down converter in the receive chain. For a band-limited signal of 98 MHz with a 20-MHz signal bandwidth, the sampling rate (Fs) of 56 Msps, the aliased component referred to 2*Fs will appear between 4MHz to 24 MHz (20 ±10 MHz.
An analog band pass filter is required at ADC input to avoid interference from other Nyquist band.


Undersampling Case of 98MHz Signal with 20MHz Bandwidth.


I designed a new breadboard with some modification. The PCB is named BBRF103 ver 0.5.


BBRF103 ver 0.5 - block diagram.

The J1 input uses a band stop filter for the FM Band 88-108 MHz.
This input is planned for experimental use within 120-500 MHz frequency range. Some specific band pass filter and LNA will be externally added for 50MHz, 144MHz or 432MHz band.


The FM Band Stop Filter - LTspice simulation.

The J2 input has a band pass filter for the FM band to analyze the full 88-108 MHz band spectrum at once. This filter is quite simpler as the FM signals are very strong versus possible interference.


FM band filter response.

Finally J3 is the HF input. The filter components values are changed from first version of BBRF103.


HF low pass filter.

The connector J4 is an optional input for an external reference signal. A capacitor must be mounted to enable this signal.

J5 and J6 are two programmable clock output from the Si5351 generator. May be used to synchronize external tuner oscillator.

RF switch type
I like to test a bi-stable subminiature DIP relay type HFD2/005-M-L2-D to switch RF instead of active switches. 
The relay is a 5Volt dual coil latched one.  I shielded it using adhesive copper tape that will be soldered to the PCB ground plane.


Relays used. The left one with a copper tape shield added.

The board scheme and PCB layout is at link http://www.steila.com/test/BBRF103_5.pdf

I preview to receive the PCB within September and then to start testing.


email: ik1xpv AT gmail DOT com




BBRF103 - Band L reception

BBRF103_2 PCB adds a switchable LNA power supply through the antenna cable

I tested it with an Outernet L-band ceramic patch antenna.  This antenna requires  power and can be connected to BBRF103_2 PCB. The antenna onboard filter helps to reduce problems from interfering signals and restricts reception to 1525 - 1559 MHz.

The antenna is a 12 by 12 cm square PCB.  I placed it into a plastic radome ( an empty IKEA FIXA series DIY kit ).



A picture of the installed radome.


Some screenshots of the band L:


Reception of Inmarsat C  with  WinSTD-C program.



Ten MHz down there are many other satellite signals.  The gap in the spectrogram shows the BBRF103 noise when the antenna power is switched off;  two spurious signals are visible on the right.

BBRF103_2 PCB notes

ADC:  I mounted the BBRF103_2 prototype with a LTC2208 ADC instead of LTC2217. I wanted to check compatibility and I had not any other LTC2217 sample. The LTC2208 is a little noiser than LTC2217 by some 2 dB.  The LTC2208 draws  some mA more current.

Antenna power: The  scheme uses 2N3906,2N3904 : Q2,Q3,Q4,Q5. The pcb footprint is wrong. Mount them upside down on the pc board.

I mounted R42,R43,R44 = 10 Ohm,  it increases the output current. 

R820T2:  I added some bypass capacitors to the VCT line on the top layer. 

Temperature: I made some measure of the temperature of R820T2 and LTC2208 with a small copper radiator.


The temperature of the ADC with a small copper radiator reaches 67 ° C while the R820T2 with the radiator reaches 45 ° C.

Preview: I will use MAX4995 50mA to 600mA Programmable Current-Limit Switch to control the LNA current in a new pcb's revision and some heat radiators will be added to ADC and RT820T2...


 email: ik1xpv AT gmail DOT com

R820T2 update - BBRF103_2 PCB

A bug crashed the USB3.0 stream at random time while the R820T2 tuner was active. ( Troubleshooting BBR103 )

It was caused by a spurious coupling via the 3V3 power supply. 

I thought of a problem in the firmware of FX3 while the cause was hardware.
I decoupled the R820T2 3V3 power supply using a separate LDO from the 5V USB bus to
solve the problem in the prototype.

The R820T can be used to receive frequency band in the range 30MHz -1800MHz.
The tuner uses a clock generated by Si5351A at 32.000MHz, the REGDIV bit of reg 4 is set to 1 to divide it by two internally to the nominal 16MHz.
The IF output is selected at 5MHz ( I used up to 7.5MHz) and it’s sampled by the ADC at 64Msps and then decimated down to 8Msps or less. The R820T data sheet states that the standard IF filters are implemented for 6/7/8 MHz channel bandwidths.

The LNA, the mixer and the VGA gains can be set manually although their precise values are absent from the datasheet.
They can also be set automatically via automatic gain control (AGC) in order to optimize the signal to noise ratio (SNR).

A revision of PCB  BBRF103_2 has been designed: ( www.steila.com/test/BBRF103_2B.pdf )

- A separate LDO voltage regulator for R820T2 has been added

- 1000 uF capacitors with a mosfet delayed switch has been added to 5VBUS and 3V3 R820T2.

- Antenna power supply with software switch added to HF and VHF input

- SMD pad dimensions have been increased a little bit to simplify manual assembly.

- Board profile modified to house SMA connectors. 

- BAV99 smd layout corrected.

- A header P7 with some GPIOs added.

- Possibility of external frequency reference input to Si5351a  ( P8 ).

- Aux clock ouput  (P9).


I just received the manufactured pcb and possibly I will test it in the next month.



BBRF103 and ExtIO.dll ver. 0.96 get 32 MHz span


End of September 2017 I was googling “SDR and FX3” when I found a nice SDR project named Booya SDR (http://booyasdr.sourceforge.net/BooyaSDRDoc.pdf , http://booyasdr.sourceforge.net/).

It uses the same USB3 Cypress Explorer Kit Board while the ADC is a LTC2206.
Reginald Eisenblatt, gave a presentation on the BooyaSDR ( January 23, 2017, at Linaspace see http://www.amrad.org/ ).
Some video at https://www.youtube.com/watch?v=uF6y0ETTJFA , notice the Waterfall with multiple rows!

The BooyaSDR application is very clever. It uses gcc compiler with pthreads and fftw library. The FX3 firmware is loaded at run time using the Cypress download protocol.

I decided to use the same software environment and compiler to test a version of ExtIO_sddc.dll for BBRF103 with pthreads lib.

To install CodeBlocks 12.11 IDE , https://sourceforge.net/projects/codeblocks/files/Binaries/12.11/Windows/  download codeblocks-12.11mingw-setup.exe  -> Default installer WITH compiler (MinGW).

ExtIO_sddc.dll ver 0.96 project links to the following libraries:
pthreads :
copy Pre-built.2 directory contens into /lib/pthreads/.

a gcc compiled version of CyAPI.cpp.
library source can be downloaded at http://www.cypress.com/file/289981/download
(see License) .

The directories structure I used is:

ExtIO_sddc \                            readme.txt ,
ExtIO_sddc \BBRF103_SE         FX3 firmware,
ExtIO_sddc \source\                 sources, ExtIO_sddc.cbp,
ExtIO_sddc \Lib\fftw                 fftw library,
ExtIO_sddc \Lib\pthreads          pthreads library ,
ExtIO_sddc \Lib\CyAPI_gcc       CyAPI gcc library ,
ExtIO_sddc \bin\debug             debug ExtIO_sddc.dll, HDSDR ,
ExtIO_sddc \bin\release            release ExtIO_sddc.dll, HDSDR.

The bin\release and \bin\debug  directories contain:

ExtIO_sddc.dll                         release or debug
BBRF103_SE.img                     BBRF103 firmware image

Sources repository :  


An archive file of project with compiled binaries can be download at


MD5    6efcd88bdc14107389cae5d6f7efe3dc

SHA-1 88ef3f3ba6276da694f6e92ebb71d987046de100


The BBR103 has been updated to version 0.2 with the following patch.
- RAND patch: a wire has been added to control the RAND pin of ADC using GPIO20 of FX3.
This option allows the control and test of RAND feature of ADC (see pg 14, 24 of http://cds.linear.com/docs/en/datasheet/2217f.pdf).
The wire connects RAND (U3-pin 63, R7,R9) to GPIO20 ( BGA K7 = PIN25 J6 FX3 SS kit).


The Firmware source can be found into the archive file of project under \Firmware directory


The 0.96 version is still a preliminary release with some bugs. It operates in HF mode only.

Problems remain in use of R820T2 tuner, and a  post on this argument will follow.

The digital signal processing frontend uses a the Halfcomplex-format DFT (http://www.fftw.org/fftw3_doc/The-Halfcomplex_002dformat-DFT.html).

The FFT output is sent to HDSDR with a selectable rate of 32 Msps or a decimated one at 16, 8, 4, 2 Msps.


Filtering and tuning is made using overlap and add with frame of 1024 as 768 +256 samples. The filter time responses are 257 sample long.

When 32Msps is used the local oscillator of HDSDR is fixed to 16 MHz at centre of spectrum and the fine tuning of HDSDR allows reception from 500 kHz to 31500 kHz, while with lower sample rates the local oscillator can be tuned with 125 kHz step while the fine tuning is made by HDSDR.

At this development stage ExtIO_sddc.dll has a GUI dialog with 4 tabs :

  • Status - reports ADC rate and I&Q rate.
  • BBRF103 -  buttons : 

LW-MW this is used to modify the FFT output filtering to receive the low frequency band.
HF - standard HF setup .
VHF - enables R820T2 ( it is disabled, to enable undefine _NO_TUNER_ in config.h and recompile)
DITH - enables the ADC dither.
RAND - enables the ADC randomize.

TRACE - enabled in debug mode  to trace some signals to log files.

  • Test

RF ADC stream: it requires BB103, ADC input ,default,
RF virtual tone: it requires BB103, virtual tone,
RF virtual sweep: it requires BB103, virtual sweep,
IF virtual tone: NO hardware required, virtual tone ,
IF virtual sweep: NO hardware required, virtual sweep,

  • About

 Hereafter a video recorded with  a random wire antenna 5mt long on the balcony (in the city).

Some variations of ExtIO_sddc.dll architecture

During Summer holidays I experimented about decimation scheme of BreadBoard RF103.

The ExtIO_sddc.dll processes the ADC real signal stream. The sampling rate is 64 MHz.
The output is a decimated I&Q complex signal stream at 16 MHz, 8MHz, 4MHz or 2MHz.
Filtering and tuning are integrated.


The dll uses CyAPI library to connect BBRF103 hardware via USB3.0.
A USBthreadProc thread uses 16 buffers queue to receive data chunk of 65536 samples (short).
One buffer’s time duration is about 1 ms at 64 MHz.
I configured USBthreadProc to run at high priority to be responsive to hardware timing.
The USBthreadProc output buffer is processed by the class RFddc that has an own buffer array of 16 elements.
The time of a circular turn of 16 buffers queue allows the digital down conversion algorithm of each chunk to complete on a separate thread.
The previously computed output vector is returned while the signal processing of the buffer is started. A priority for these threads below normal seems good enough.
Frequency domain signal processing is used. An overlap and add FFT scheme processes the buffer 65536 sample frame and overlap and save scheme glues the buffers together.

The following diagram represents the processing of one buffer frame and it is implemented in every thread of the RFddc pool of 16.



1) It is the input sample array of short. It is a real signal. The frame buffer is a sequence of 65536 samples (it can be seen as a sequence of 64 *1024 slice).

2) The last 1024 slice in the past is copied at the beginning of the array to form a frame of 65 *1024 = 66560 samples. This is the overlap and save scheme.

3) A complex array 66560 samples long is obtained from (2) adding a zero imaginary component.

4) Starting from 0 the array is divided into slices of 768 samples to implement override and add (Overlap and add method)  with an overlap of 256 and a fast Fourier transform (FFT) of 1024 sample frame.

5) Every 768 slice is copied into a 1024 one adding a tail of 256 sample zero filled.
85 slice of 1024 complex samples.

6) A FFT forward is applied to the every 1024 slice. 85 slices in frequency domain are computed.

7) For every slide a circular shift of the FFT’s bins is used to implement tuning to the IQ carrier frequency.
The resolution is 64000000/1024 = 62500 Hz. This coarse step is good enough for HDSDR tuning that uses its own fine adjustment. A phase adjustment is required depending on the tuning bin position.

8) A low pass filter of the signal is implemented as fast convolution (https://en.wikipedia.org/wiki/Convolution#Fast_convolution_algorithms) multiplying the FFT bins by the complex conjugate (https://en.wikipedia.org/wiki/Complex_conjugate) frequency response of the filter (Hw*). To use the fast convolution approach the length of the time filter response ht is limited to (1024 -768) +1 = 257 samples.

9) Decimation in frequency is used. The implemented output lengths are 256,128,64,32 that obtains output rate of 16MHz, 8MHz, 4MHz, 2MHz. It is made just copying the decimated FFT bins chunk near zero frequency.

10) The resulting output is a sequence of decimated FFT ( 256,…) bins. Steps (7) (8) (9) are implemented together in a copy and modify loop.

11) The 85 slices of decimated FFT.

12) The FFT inverse is computed.

13) The time output is computed with overlap and add of the 85 slices. The first 256 samples and the latest 512 are dropped using overlap and save (Overlap save method)  of the 64 * decimated FFTN samples frames.
The function has an array of 65536 samples input and returns an array of 16.384 samples at 16MHz, 8.192 at 8MHz, 4.096 at 4MHz, 2.048 at 2MHz.
A separate thread processes the signal from each one buffer.


CPU use of HDSDR and ExtIO_sddc, V0.95 ADC 64MHz, IQ 16Msps ; 60 s plot

I made some debug measuring the time jitter of USBthreadProc 16 buffer cycle.
The theoretical time is 16 * 1.024 ms = 16.384 ms.
Here after a plot of the measured duration time - 16.384 ms.
The plot shows that the peak jitter is within +/- 3mS.



USBthreadProc 16 buffer circle timing jitter running at 64 MHz in 16MHz sampling output, 60 s plot.

I named this release version 0.95 and I save it in a separate GitHub repository at:


I switched to the integrated Visual studio Git and it was simpler to me to keep it separate from other BBRF103 project components.


To be continued.