# PScope a useful tool

To refine and measure the hardware and software performance of SDRs similar to BBRF103 there is an excellent software tool developed at the time by Linear Technology, today Analog Devices.

PScope allows you to quickly evaluate the performance of ADC chips.

I recommend the web page PScope: High-Speed ADC Data Collection Software on the Analog site where there is also a link to download installation file http://ltspice.analog.com/software/ltcps.exe it is free.

The video is also on youtube

The application has a help file and Analog Devices presents a PScope-Basics  page.

When used with ADC development boards the program requires specific drivers but can be installed without any driver.
It is possible to input the data we want to measure through a file that has a specific format that I tried to emulate by replicating the header of the file.
The files have the extension .adc
Our program, in my case ExtIO.dll will call my PScopeShot function specifying the name of the file that will be created, a title, a short description, the sample rate, the data pointer, their length.

I'm trying to figure out if the performance of my RF103 prototype (an HF-only version of BBRF103 with minor modifications) can be improved in hardware or software.

In the Extio.dll in the debugging configuration I have activated the possibility to replace the data generated by the ADC with a virtual buffer that contains the samples of a 16 bit sinusoid sampled and explored at the desired frequency.

In the initialization procedure of the dll I added the code:

…#ifndef _NO_PScope_ACTIVE_/* Virtual sine generator test PScope*/ unsigned int kidx = 0; float samplerate = adcfixedfreq; unsigned int mdf = Xfreq * ((double) 65386000.0/samplerate); // freq correction short* testdata = (short *) malloc(RF_TABLE_SIZE * sizeof( short)); // test buffer data unsigned int numsamples = global.transferSize/sizeof(short); for (unsigned int n =0; n < numsamples; n++ ) {   kidx %= RF_TABLE_SIZE;   testdata[n] = sine_table_16bit[kidx] ;   kidx += mdf; } PScopeShot("VirtualSineWave.adc", "RF103_7a", "VirtualSineWave.adc input virtual test 16 bit sine", testdata, samplerate, numsamples ); free (testdata);#endif // _PScope_ACTIVE_...

The PscopeShot procedure is defined as

int PScopeShot(const char * filename, const char * title2, const char * title1, short * data, float samplerate, unsigned int numsamples ){ FILE *fp; fp = fopen(filename, "w+"); fputs("Version,115\n", fp); fprintf(fp, "Retainers,0,1,%d,1024,0,%f,1,1\n",numsamples,samplerate ); fputs("Placement,44,0,1,-1,-1,-1,-1,88,40,1116,879", fp); fputs("WindMgr,7,2,0\n", fp); fputs("Page,0,2\n", fp); fputs("Col,3,1\n", fp); fputs("Row,2,1\n", fp); fputs("Row,3,146\n", fp); fputs("Row,1,319\n", fp); fputs("Col,2,1063\n", fp); fputs("Row,4,1\n", fp); fputs("Row,0,319\n", fp); fputs("Page,1,2\n", fp); fputs("Col,1,1\n", fp); fputs("Row,1,1\n", fp); fputs("Col,2,425\n", fp); fputs("Row,4,1\n", fp); fputs("Row,0,319\n", fp); fprintf(fp,"DemoID,%s,%s,0\n", title1, title2 ); fprintf(fp,"RawData,1,%d,16,-32768,32767,%f,-3.276800e+04,3.276800e+04\n", numsamples,samplerate); for (unsigned int n = 0; n < numsamples; n++ )  {    fprintf(fp, "%d\n", data[n]);  } fputs("end\n", fp); return fclose(fp);}

The acquired file of the virtual generator signal when loaded in PScope File menu draws:

No bad for a 16bit software table lookup implementation!

Here the picture of the HDSDR output when we select the RF virtual tone generator. It’s very similar to PScope analysis and result.

In a second test I forced the software DDC input samples to a constant value, a DC component.

… short anyvalue = 0x5aC3; for (unsigned int n =0; n < numsamples; n++ ) { testdata[n] = anyvalue; } PScopeShot("VirtualDClevel.adc", "RF103_7a", "VirtualDClevel.adc input virtual test DC value", testdata, samplerate, numsamples );…

The PScope analysis shows no noise component as we have a perfect stable input virtual level.

SNR not available as there as noise is absent.

In the HDSDR world we get:

This only verifies that there are no noise components added by the DDC.

## BBRF103  posts

Some variations of ExtIO_sddc.dll architecture        31 August, 2017

Troubleshooting BBR103          22 September, 2017

BBRF103 and ExtIO.dll ver. 0.96 get 32 MHz span    1 March, 2018

R820T2 update - BBRF103_2 PCB           10 April, 2018

BBRF103 - Band L reception                   26 May, 2018

Just another BBRF103 version                14 August, 2018

BBRF103-2 RC3 is here!                         1 September, 2018

BBRF103 Construction notes                   4 May, 2019

BBRF103 Some measurements               20 May, 2019

Receivers similar to BBRF103 ?               08 June, 2020

PScope a useful tool                              19 June, 2020

# Receivers similar to BBRF103 ?

Some receivers with an architecture similar to BBRF103 appeared in the web during this look down time.
I tried to contact the authors not for copyright issues, being BBRF103 completely open source but to exchange some experiences. A contacted person wrote me that the project is new and fully original, but I think I reached the re-seller and not the designer.
So I signal my interest in talking with the real authors of the devices.
I list the devices with links to images that are in these weeks at the following links.

If someone has a review or any other info please send it to me.

Thanks, everyone,  ik1xpv AT gmail DOT com

Update 15 August, 2020

- If you want to give a try to BBRF103 software with these receivers, here the compiled ExtIO_sddc.dll : v.0.96 (HF only) and v.0.98 (HF and VHF).

Update 19 August, 2020

- The RX888 SDR – Up Close Photos at  https://swling.com/blog/2020/08/the-rx888-sdr-up-close-photos/

- The RX-888 Team sent me the link to they RX-888 software at

source:

# RX-666 ?

source:

https://img.alicdn.com/imgextra/i2/22088642/O1CN01wrOfUF2Di5PDC8KRa_!!22088642.jpg

https://img.alicdn.com/imgextra/i4/22088642/O1CN017bLC3v2Di5OpbZuEj_!!22088642.jpg

https://img.alicdn.com/imgextra/i3/22088642/O1CN01B86EWy2Di5P6pKtn4_!!22088642.jpg

https://img.alicdn.com/imgextra/i3/22088642/O1CN01hqZ7N92Di5OrG2ydq_!!22088642.jpg

## BBRF103  posts

Some variations of ExtIO_sddc.dll architecture        31 August, 2017

Troubleshooting BBR103          22 September, 2017

BBRF103 and ExtIO.dll ver. 0.96 get 32 MHz span    1 March, 2018

R820T2 update - BBRF103_2 PCB           10 April, 2018

BBRF103 - Band L reception                  26 May, 2018

Just another BBRF103 version                  14 August, 2018

BBRF103-2 RC3 is here!                         1 September, 2018

BBRF103 Construction notes                   4 May, 2019

BBRF103 Some measurements               20 May, 2019

Receivers similar to BBRF103 ?               08 June, 2020

PScope a useful tool               19 June, 2020

# BBRF103 Construction notes

These days I assembled a second prototype of BBRF103 receiver.  Here are some notes.

### Power supply

I made a different power harness. The purpose is to allow the circuit to be powered by the USB cable with VBUS or via a separate 5Volt power connector.

So far in the diagrams of BBRF103 the input of the 5V power supply to the PCB is taken from the VBUS of CYUSB3KIT-003.

I noticed on my two prototypes some problem related to the intervention of the protection circuit (U11 sheet 2 of 8, CYUSB3KIT scheme) on the Cypress plate and caused by the current increase required in some phases of power-up of the PCB BBRF103 and R820T2 use.

I modified the input of the 5Volt and connected it upstream of the protection circuit using the J3 jumper as a connector.

The scheme is as follows:

The current consumption of complete BBRF103 using Tuner R820T2 is about 530mA at 5Vdc.

From left to right

- 5Volt dc external input (optional)

- latched pushbutton VBUS / extenal 5V

- USB3 connector

- ON / OFF

### Shielding box

The box used is made of aluminum, it has dimensions 100x76x35mm, currently at Banggood it is available only in a golden color. The surface is brushed and treated with an insulating process so it is necessary to sandpaper the contact surfaces to obtain an electrical contact when it closes.

In the grooves on the long sides I inserted after scratching the rail a strip of Desoldering Copper Wick as a contact gasket.

### Heat dissipation

The ADC LTC2217 and the tuner R820T dissipate more than one Watt in heat. To keep the temperature of the chips lower, I tried two passive aluminium heat sinks that lead the heat to the aluminium box, which acts as a heat sink, reducing the temperature of the chips by 20-30° C.

The radiators are fixed with some M2 nylon insulating screws and nuts. I used a slightly modified PCB from BBRF103-2 layout.

### Stand alone static current test

Assembling the pcb I have tried a simple method to verify errors of power supply rails.

Each block of the circuit is powered separately through a filter inductor. So not mounting these components it is easy to measure the current absorbed by various blocks on the PCB BBRF103-2 before connecting the CYUSB3KIT-003 board.

Here is a table with the measured power consumption of three blocks in a static way.
I have not mounted FL1, FL2, FL3.
I connected a 5Volt /500mA power supply to the LDO power supply of the plate and
I measured the current at the unassembled inductors by injecting an external voltage, getting:

 Block Current Measuring point Oscillator SI5351 15-16 mA FL3 / external power supply 3.3V Tuner R820T2 80-85 mA FL2 / external power supply 3.3V ADC LTC2217 269-210 mA FL1 / external power supply 5V (ADC gets 3.3V via LDO)

In case, inspect the component mounting and check the welds with a microscope or lens.

# BBRF103-2 RC3 is here!

Radek Haša is a shortwave and airband listener living in Czech republic.
He decided to redesign the PCB layout and assembled a prototype of the BBRF103-2.
Thanks for allowing his project to be published.

While designing the PCB in Eagle 8.x format, he noticed and fixed some bugs in my layout.

- Referring to transformers T1,T2,T3. The Coilcraft WBC4-6TL type is better than the WBC4-1TL. The insertion loss is 0.65 dB instead of 1 dB. (WBC datasheet)
Note that terminals 4 and 6 of the primary winding are interchanged in the electric scheme and the SMD footprint used in the PCB. This does not affect performance and will be corrected in the future PCB version to match the original SMD footprint.

- The Q1,Q2,Q3,Q4 SMD footprint is corrected in RC3 PCB.

- C44 and C55 silkscreen locations are swapped in the BBRF103-2 original PCB. Footprint is corrected in RC3 PCB layout.

Prototype was tested on desktop PC equipped with Intel Pentium G4600 CPU and B150 chipset USB 3.0 hub controller. Hereafter some pictures of prototype under testing.

He made some test of temperature of the ADC and R820T2 in VHF mode.
“There are no heatsinks on ADC and R820T2. The temperature of the ADC reached 73 ° C while the R820T2 reached 60 ° C at 100MHz. Room temperature was 27 ° C.“

WARNING: notice that this description is a BETA test version without any warranty and is intended for non-commercial purposes.

The archive contains:
BBRF103-RC3.sch
BBRF103-RC3.brd
BBRF103.ods

Finally please notice that ExtIOsddc.dll ver 0.96 software does not yet control the antenna power via dll panel window and to enable VHF (R820T2) mode you must undefine _NO_TUNER_ in config.h and recompile.

email: ik1xpv AT gmail DOT com

# Some variations of ExtIO_sddc.dll architecture

The ExtIO_sddc.dll processes the ADC real signal stream. The sampling rate is 64 MHz.
The output is a decimated I&Q complex signal stream at 16 MHz, 8MHz, 4MHz or 2MHz.
Filtering and tuning are integrated.

The dll uses CyAPI library to connect BBRF103 hardware via USB3.0.
One buffer’s time duration is about 1 ms at 64 MHz.
I configured USBthreadProc to run at high priority to be responsive to hardware timing.
The USBthreadProc output buffer is processed by the class RFddc that has an own buffer array of 16 elements.
The time of a circular turn of 16 buffers queue allows the digital down conversion algorithm of each chunk to complete on a separate thread.
The previously computed output vector is returned while the signal processing of the buffer is started. A priority for these threads below normal seems good enough.
Frequency domain signal processing is used. An overlap and add FFT scheme processes the buffer 65536 sample frame and overlap and save scheme glues the buffers together.

The following diagram represents the processing of one buffer frame and it is implemented in every thread of the RFddc pool of 16.

notes:

1) It is the input sample array of short. It is a real signal. The frame buffer is a sequence of 65536 samples (it can be seen as a sequence of 64 *1024 slice).

2) The last 1024 slice in the past is copied at the beginning of the array to form a frame of 65 *1024 = 66560 samples. This is the overlap and save scheme.

3) A complex array 66560 samples long is obtained from (2) adding a zero imaginary component.

4) Starting from 0 the array is divided into slices of 768 samples to implement override and add (Overlap and add method)  with an overlap of 256 and a fast Fourier transform (FFT) of 1024 sample frame.

5) Every 768 slice is copied into a 1024 one adding a tail of 256 sample zero filled.
85 slice of 1024 complex samples.

6) A FFT forward is applied to the every 1024 slice. 85 slices in frequency domain are computed.

7) For every slide a circular shift of the FFT’s bins is used to implement tuning to the IQ carrier frequency.
The resolution is 64000000/1024 = 62500 Hz. This coarse step is good enough for HDSDR tuning that uses its own fine adjustment. A phase adjustment is required depending on the tuning bin position.

8) A low pass filter of the signal is implemented as fast convolution (https://en.wikipedia.org/wiki/Convolution#Fast_convolution_algorithms) multiplying the FFT bins by the complex conjugate (https://en.wikipedia.org/wiki/Complex_conjugate) frequency response of the filter (Hw*). To use the fast convolution approach the length of the time filter response ht is limited to (1024 -768) +1 = 257 samples.

9) Decimation in frequency is used. The implemented output lengths are 256,128,64,32 that obtains output rate of 16MHz, 8MHz, 4MHz, 2MHz. It is made just copying the decimated FFT bins chunk near zero frequency.

10) The resulting output is a sequence of decimated FFT ( 256,…) bins. Steps (7) (8) (9) are implemented together in a copy and modify loop.

11) The 85 slices of decimated FFT.

12) The FFT inverse is computed.

13) The time output is computed with overlap and add of the 85 slices. The first 256 samples and the latest 512 are dropped using overlap and save (Overlap save method)  of the 64 * decimated FFTN samples frames.
The function has an array of 65536 samples input and returns an array of 16.384 samples at 16MHz, 8.192 at 8MHz, 4.096 at 4MHz, 2.048 at 2MHz.
A separate thread processes the signal from each one buffer.

CPU use of HDSDR and ExtIO_sddc, V0.95 ADC 64MHz, IQ 16Msps ; 60 s plot

I made some debug measuring the time jitter of USBthreadProc 16 buffer cycle.
The theoretical time is 16 * 1.024 ms = 16.384 ms.
Here after a plot of the measured duration time - 16.384 ms.
The plot shows that the peak jitter is within +/- 3mS.

USBthreadProc 16 buffer circle timing jitter running at 64 MHz in 16MHz sampling output, 60 s plot.

I named this release version 0.95 and I save it in a separate GitHub repository at:

https://github.com/ik1xpv/ExtIO_sddc

I switched to the integrated Visual studio Git and it was simpler to me to keep it separate from other BBRF103 project components.

To be continued.

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