ik1xpv hamradio software & hardware

BBRF103 - Band L reception

BBRF103_2 PCB adds a switchable LNA power supply through the antenna cable

I tested it with an Outernet L-band ceramic patch antenna.  This antenna requires  power and can be connected to BBRF103_2 PCB. The antenna onboard filter helps to reduce problems from interfering signals and restricts reception to 1525 - 1559 MHz.

The antenna is a 12 by 12 cm square PCB.  I placed it into a plastic radome ( an empty IKEA FIXA series DIY kit ).



A picture of the installed radome.


Some screenshots of the band L:


Reception of Inmarsat C  with  WinSTD-C program.



Ten MHz down there are many other satellite signals.  The gap in the spectrogram shows the BBRF103 noise when the antenna power is switched off;  two spurious signals are visible on the right.

BBRF103_2 PCB notes

ADC:  I mounted the BBRF103_2 prototype with a LTC2208 ADC instead of LTC2217. I wanted to check compatibility and I had not any other LTC2217 sample. The LTC2208 is a little noiser than LTC2217 by some 2 dB.  The LTC2208 draws  some mA more current.

Antenna power: The  scheme uses 2N3906,2N3904 : Q2,Q3,Q4,Q5. The pcb footprint is wrong. Mount them upside down on the pc board.

I mounted R42,R43,R44 = 10 Ohm,  it increases the output current. 

R820T2:  I added some bypass capacitors to the VCT line on the top layer. 

Temperature: I made some measure of the temperature of R820T2 and LTC2208 with a small copper radiator.


The temperature of the ADC with a small copper radiator reaches 67 ° C while the R820T2 with the radiator reaches 45 ° C.

Preview: I will use MAX4995 50mA to 600mA Programmable Current-Limit Switch to control the LNA current in a new pcb's revision and some heat radiators will be added to ADC and RT820T2...



R820T2 update - BBRF103_2 PCB

A bug crashed the USB3.0 stream at random time while the R820T2 tuner was active. ( Troubleshooting BBR103 )

It was caused by a spurious coupling via the 3V3 power supply. 

I thought of a problem in the firmware of FX3 while the cause was hardware.
I decoupled the R820T2 3V3 power supply using a separate LDO from the 5V USB bus to
solve the problem in the prototype.

The R820T can be used to receive frequency band in the range 30MHz -1800MHz.
The tuner uses a clock generated by Si5351A at 32.000MHz, the REGDIV bit of reg 4 is set to 1 to divide it by two internally to the nominal 16MHz.
The IF output is selected at 5MHz ( I used up to 7.5MHz) and it’s sampled by the ADC at 64Msps and then decimated down to 8Msps or less. The R820T data sheet states that the standard IF filters are implemented for 6/7/8 MHz channel bandwidths.

The LNA, the mixer and the VGA gains can be set manually although their precise values are absent from the datasheet.
They can also be set automatically via automatic gain control (AGC) in order to optimize the signal to noise ratio (SNR).

A revision of PCB  BBRF103_2 has been designed: ( www.steila.com/test/BBRF103_2B.pdf )

- A separate LDO voltage regulator for R820T2 has been added

- 1000 uF capacitors with a mosfet delayed switch has been added to 5VBUS and 3V3 R820T2.

- Antenna power supply with software switch added to HF and VHF input

- SMD pad dimensions have been increased a little bit to simplify manual assembly.

- Board profile modified to house SMA connectors. 

- BAV99 smd layout corrected.

- A header P7 with some GPIOs added.

- Possibility of external frequency reference input to Si5351a  ( P8 ).

- Aux clock ouput  (P9).


I just received the manufactured pcb and possibly I will test it in the next month.



BBRF103 and ExtIO.dll ver. 0.96 get 32 MHz span


End of September 2017 I was googling “SDR and FX3” when I found a nice SDR project named Booya SDR (http://booyasdr.sourceforge.net/BooyaSDRDoc.pdf , http://booyasdr.sourceforge.net/).

It uses the same USB3 Cypress Explorer Kit Board while the ADC is a LTC2206.
Reginald Eisenblatt, gave a presentation on the BooyaSDR ( January 23, 2017, at Linaspace see http://www.amrad.org/ ).
Some video at https://www.youtube.com/watch?v=uF6y0ETTJFA , notice the Waterfall with multiple rows!

The BooyaSDR application is very clever. It uses gcc compiler with pthreads and fftw library. The FX3 firmware is loaded at run time using the Cypress download protocol.

I decided to use the same software environment and compiler to test a version of ExtIO_sddc.dll for BBRF103 with pthreads lib.

To install CodeBlocks 12.11 IDE , https://sourceforge.net/projects/codeblocks/files/Binaries/12.11/Windows/  download codeblocks-12.11mingw-setup.exe  -> Default installer WITH compiler (MinGW).

ExtIO_sddc.dll ver 0.96 project links to the following libraries:
pthreads :
copy Pre-built.2 directory contens into /lib/pthreads/.

a gcc compiled version of CyAPI.cpp.
library source can be downloaded at http://www.cypress.com/file/289981/download
(see License) .

The directories structure I used is:

ExtIO_sddc \                            readme.txt ,
ExtIO_sddc \BBRF103_SE         FX3 firmware,
ExtIO_sddc \source\                 sources, ExtIO_sddc.cbp,
ExtIO_sddc \Lib\fftw                 fftw library,
ExtIO_sddc \Lib\pthreads          pthreads library ,
ExtIO_sddc \Lib\CyAPI_gcc       CyAPI gcc library ,
ExtIO_sddc \bin\debug             debug ExtIO_sddc.dll, HDSDR ,
ExtIO_sddc \bin\release            release ExtIO_sddc.dll, HDSDR.

The bin\release and \bin\debug  directories contain:

ExtIO_sddc.dll                         release or debug
BBRF103_SE.img                     BBRF103 firmware image

Sources repository :  


An archive file of project with compiled binaries can be download at


MD5    6efcd88bdc14107389cae5d6f7efe3dc

SHA-1 88ef3f3ba6276da694f6e92ebb71d987046de100


The BBR103 has been updated to version 0.2 with the following patch.
- RAND patch: a wire has been added to control the RAND pin of ADC using GPIO20 of FX3.
This option allows the control and test of RAND feature of ADC (see pg 14, 24 of http://cds.linear.com/docs/en/datasheet/2217f.pdf).
The wire connects RAND (U3-pin 63, R7,R9) to GPIO20 ( BGA K7 = PIN25 J6 FX3 SS kit).


The Firmware source can be found into the archive file of project under \Firmware directory


The 0.96 version is still a preliminary release with some bugs. It operates in HF mode only.

Problems remain in use of R820T2 tuner, and a  post on this argument will follow.

The digital signal processing frontend uses a the Halfcomplex-format DFT (http://www.fftw.org/fftw3_doc/The-Halfcomplex_002dformat-DFT.html).

The FFT output is sent to HDSDR with a selectable rate of 32 Msps or a decimated one at 16, 8, 4, 2 Msps.


Filtering and tuning is made using overlap and add with frame of 1024 as 768 +256 samples. The filter time responses are 257 sample long.

When 32Msps is used the local oscillator of HDSDR is fixed to 16 MHz at centre of spectrum and the fine tuning of HDSDR allows reception from 500 kHz to 31500 kHz, while with lower sample rates the local oscillator can be tuned with 125 kHz step while the fine tuning is made by HDSDR.

At this development stage ExtIO_sddc.dll has a GUI dialog with 4 tabs :

  • Status - reports ADC rate and I&Q rate.
  • BBRF103 -  buttons : 

LW-MW this is used to modify the FFT output filtering to receive the low frequency band.
HF - standard HF setup .
VHF - enables R820T2 ( it is disabled, to enable undefine _NO_TUNER_ in config.h and recompile)
DITH - enables the ADC dither.
RAND - enables the ADC randomize.

TRACE - enabled in debug mode  to trace some signals to log files.

  • Test

RF ADC stream: it requires BB103, ADC input ,default,
RF virtual tone: it requires BB103, virtual tone,
RF virtual sweep: it requires BB103, virtual sweep,
IF virtual tone: NO hardware required, virtual tone ,
IF virtual sweep: NO hardware required, virtual sweep,

  • About

 Hereafter a video recorded with  a random wire antenna 5mt long on the balcony (in the city).