Radek Haša is a shortwave and airband listener living in Czech republic. He decided to redesign the PCB layout and assembled a prototype of the BBRF103-2. Thanks for allowing his project to be published.
While designing the PCB in Eagle 8.x format, he noticed and fixed some bugs in my layout.
- Referring to transformers T1,T2,T3. The Coilcraft WBC4-6TL type is better than the WBC4-1TL. The insertion loss is 0.65 dB instead of 1 dB. (WBC datasheet) Note that terminals 4 and 6 of the primary winding are interchanged in the electric scheme and the SMD footprint used in the PCB. This does not affect performance and will be corrected in the future PCB version to match the original SMD footprint.
- The Q1,Q2,Q3,Q4 SMD footprint is corrected in RC3 PCB.
- C44 and C55 silkscreen locations are swapped in the BBRF103-2 original PCB. Footprint is corrected in RC3 PCB layout.
Prototype was tested on desktop PC equipped with Intel Pentium G4600 CPU and B150 chipset USB 3.0 hub controller. Hereafter some pictures of prototype under testing.
He made some test of temperature of the ADC and R820T2 in VHF mode. “There are no heatsinks on ADC and R820T2. The temperature of the ADC reached 73 ° C while the R820T2 reached 60 ° C at 100MHz. Room temperature was 27 ° C.“
WARNING: notice that this description is a BETA test version without any warranty and is intended for non-commercial purposes.
Finally please notice that ExtIOsddc.dll ver 0.96 software does not yet control the antenna power via dll panel window and to enable VHF (R820T2) mode you must undefine _NO_TUNER_ in config.h and recompile.
A new board to experiment with undersampling technique.
“..If we use the sampling frequency less than twice the maximum frequency component in the signal, then it is called undersampling. Undersampling is also known as band pass sampling, harmonic sampling or super-Nyquist sampling. Nyquist-Shannon Sampling theorem, which is the modified version of the Nyquist sampling theorem, says that the sampling frequency needs to be twice the signal bandwidth and not twice the maximum frequency component, in order to be able to reconstruct the original signal perfectly from the sampled version. If B is the signal bandwidth, then Fs > 2B is required where Fs is sampling frequency. The signal bandwidth can be from DC to B or from f1 to f2 where B = f2 – f1. The aliasing effect due to the undersampling technique can be used for our advantage. When a signal is sampled at a rate less than twice its maximum frequency, the aliased signal appears at Fs – Fin, where Fs is the sampling frequency and Fin in the input signal frequency. “ from Why Use Oversampling when Undersampling Can do the Job? - Texas Instruments.
In an example case looking at FM band we sample the input 98 MHz with Fs = 56MHz and the aliased component will appear at 14 MHz ( 56*2 – 98). As we know in advance that the signal is aliased, we can recover the actual frequency by using the N*Fs – Fin relationship. The undersampling technique allows the ADC to behave like a mixer or a down converter in the receive chain. For a band-limited signal of 98 MHz with a 20-MHz signal bandwidth, the sampling rate (Fs) of 56 Msps, the aliased component referred to 2*Fs will appear between 4MHz to 24 MHz (20 ±10 MHz. An analog band pass filter is required at ADC input to avoid interference from other Nyquist band.
Undersampling Case of 98MHz Signal with 20MHz Bandwidth.
I designed a new breadboard with some modification. The PCB is named BBRF103 ver 0.5.
BBRF103 ver 0.5 - block diagram.
The J1 input uses a band stop filter for the FM Band 88-108 MHz. This input is planned for experimental use within 120-500 MHz frequency range. Some specific band pass filter and LNA will be externally added for 50MHz, 144MHz or 432MHz band.
The FM Band Stop Filter - LTspice simulation.
The J2 input has a band pass filter for the FM band to analyze the full 88-108 MHz band spectrum at once. This filter is quite simpler as the FM signals are very strong versus possible interference.
FM band filter response.
Finally J3 is the HF input. The filter components values are changed from first version of BBRF103.
HF low pass filter.
The connector J4 is an optional input for an external reference signal. A capacitor must be mounted to enable this signal.
J5 and J6 are two programmable clock output from the Si5351 generator. May be used to synchronize external tuner oscillator.
RF switch type I like to test a bi-stable subminiature DIP relay type HFD2/005-M-L2-D to switch RF instead of active switches. The relay is a 5Volt dual coil latched one. I shielded it using adhesive copper tape that will be soldered to the PCB ground plane.
Relays used. The left one with a copper tape shield added.
BBRF103_2 PCB adds a switchable LNA power supply through the antenna cable
I tested it with an Outernet L-band ceramic patch antenna. This antenna requires power and can be connected to BBRF103_2 PCB. The antenna onboard filter helps to reduce problems from interfering signals and restricts reception to 1525 - 1559 MHz.
Ten MHz down there are many other satellite signals. The gap in the spectrogram shows the BBRF103 noise when the antenna power is switched off; two spurious signals are visible on the right.
BBRF103_2 PCB notes
ADC:I mounted the BBRF103_2 prototype with a LTC2208 ADC instead of LTC2217. I wanted to check compatibility and I had not any other LTC2217 sample. The LTC2208 is a little noiser than LTC2217 by some 2 dB. The LTC2208 draws some mA more current.
Antenna power: The scheme uses 2N3906,2N3904 : Q2,Q3,Q4,Q5. The pcb footprint is wrong. Mount them upside down on the pc board.
I mounted R42,R43,R44 = 10 Ohm, it increases the output current.
R820T2: I added some bypass capacitors to the VCT line on the top layer.
Temperature: I made some measure of the temperature of R820T2 and LTC2208 with a small copper radiator.
The temperature of the ADC with a small copper radiator reaches 67 ° C while the R820T2 with the radiator reaches 45 ° C.
Preview: I will use MAX4995 50mA to 600mA Programmable Current-Limit Switch to control the LNA current in a new pcb's revision and some heat radiators will be added to ADC and RT820T2...
It was caused by a spurious coupling via the 3V3 power supply.
I thought of a problem in the firmware of FX3 while the cause was hardware. I decoupled the R820T2 3V3 power supply using a separate LDO from the 5V USB bus to solve the problem in the prototype.
The R820T can be used to receive frequency band in the range 30MHz -1800MHz. The tuner uses a clock generated by Si5351A at 32.000MHz, the REGDIV bit of reg 4 is set to 1 to divide it by two internally to the nominal 16MHz. The IF output is selected at 5MHz ( I used up to 7.5MHz) and it’s sampled by the ADC at 64Msps and then decimated down to 8Msps or less. The R820T data sheet states that the standard IF filters are implemented for 6/7/8 MHz channel bandwidths.
The LNA, the mixer and the VGA gains can be set manually although their precise values are absent from the datasheet. They can also be set automatically via automatic gain control (AGC) in order to optimize the signal to noise ratio (SNR).
It uses the same USB3 Cypress Explorer Kit Board while the ADC is a LTC2206. Reginald Eisenblatt, gave a presentation on the BooyaSDR ( January 23, 2017, at Linaspace see http://www.amrad.org/ ). Some video at https://www.youtube.com/watch?v=uF6y0ETTJFA , notice the Waterfall with multiple rows!
The BooyaSDR application is very clever. It uses gcc compiler with pthreads and fftw library. The FX3 firmware is loaded at run time using the Cypress download protocol.
I decided to use the same software environment and compiler to test a version of ExtIO_sddc.dll for BBRF103 with pthreads lib.
The BBR103 has been updated to version 0.2 with the following patch. - RAND patch: a wire has been added to control the RAND pin of ADC using GPIO20 of FX3. This option allows the control and test of RAND feature of ADC (see pg 14, 24 of http://cds.linear.com/docs/en/datasheet/2217f.pdf). The wire connects RAND (U3-pin 63, R7,R9) to GPIO20 ( BGA K7 = PIN25 J6 FX3 SS kit).
The Firmware source can be found into the archive file of project under \Firmware directory
The 0.96 version is still a preliminary release with some bugs. It operates in HF mode only.
Problems remain in use of R820T2 tuner, and a post on this argument will follow.
The FFT output is sent to HDSDR with a selectable rate of 32 Msps or a decimated one at 16, 8, 4, 2 Msps.
Filtering and tuning is made using overlap and add with frame of 1024 as 768 +256 samples. The filter time responses are 257 sample long.
When 32Msps is used the local oscillator of HDSDR is fixed to 16 MHz at centre of spectrum and the fine tuning of HDSDR allows reception from 500 kHz to 31500 kHz, while with lower sample rates the local oscillator can be tuned with 125 kHz step while the fine tuning is made by HDSDR.
At this development stage ExtIO_sddc.dll has a GUI dialog with 4 tabs :
Status - reports ADC rate and I&Q rate.
BBRF103 - buttons :
LW-MW this is used to modify the FFT output filtering to receive the low frequency band. HF - standard HF setup . VHF - enables R820T2 ( it is disabled, to enable undefine _NO_TUNER_ in config.h and recompile) DITH - enables the ADC dither. RAND - enables the ADC randomize.
TRACE - enabled in debug mode to trace some signals to log files.
RF ADC stream: it requires BB103, ADC input ,default, RF virtual tone: it requires BB103, virtual tone, RF virtual sweep: it requires BB103, virtual sweep, IF virtual tone: NO hardware required, virtual tone , IF virtual sweep: NO hardware required, virtual sweep,
Hereafter a video recorded with a random wire antenna 5mt long on the balcony (in the city).
"Troubleshooting or dépanneuring is a form of problem solving, often applied to repair failed products or processes on a machine or a system. It is a logical, systematic search for the source of a problem in order to solve it, and make the product or process operational again. Troubleshooting is needed to identify the symptoms. Determining the most likely cause is a process of elimination—eliminating potential causes of a problem. Finally, troubleshooting requires confirmation that the solution restores the product or process to its working state." (from:https://en.wikipedia.org/wiki/Wikipedia:Troubleshooting).
BBR103 prototype is alive, nevertheless some bugs limit the performance. Hereafter the syntoms and some investigation to hopefully solve them.
I focused on the HF operation using HDSDR with IF bandwidth of 16 MHz as shown in the following picture.
The BBR103 in the picture is connected to a 5 meter wire on my balcony in the city. The ADC performance seems good as espected.
Nevertheless I notice the following problems during its use:
001) (SOLVED) The signals had a periodic distortion (-50 dB down) at 10ms time distance. I noticed it using a 10MHz reference generator.
The bug was periodic with the period of the FRAMEN lenght buffer. Digging in the rfddc code I got the bug. It was mirroring the wrong past frame.
002) There are some distortion on the signal that are at random time like the following I got in a IQ waveform recorded with HDSDR.
The distortion looks like a 90° phase shift. I imagine that the cause is in the dll. The randomness of the behaviour keeps the search difficult.
003) The USB communication fails at random time (up to some tens minutes). I got the following debug message:
Xfer request rejected. NTSTATUS = c000000e
The USB device disconnects. It requires reset to start again.
My knowledge about USB is very low and I have to learn everything. I found some hits:
2) Run HDSDR and then close it ( to initialize the BBRF103 hardware).
3) Run the FX3USBread console application from FX3GPIFnoise.zip.
I use a script file. In this example it has a 3 minutes run.
d:\DEV\FX3GPIFnoise>time /T 03:15 PM
d:\DEV\FX3GPIFnoise>FX3USBread FX3USBread version 1.0
Press ESC for stop Count:22982361088 Speed:120.571MB/s Max:122.792MB/s DeviceIoControl failed (GetOverlappedResult error code=995) Operazione di I/O terminata a causa dell'uscita dal thread oppure della richiesta di un'applicazione.
d:\DEV\FX3GPIFnoise>time /T 03:19 PM
d:\DEV\FX3GPIFnoise>PAUSE Premere un tasto per continuare . . .
It crashes at random time as it happens with HDSDR+ ExtIO_sddc.
I made the same test using Cypress stream application.
Power on of BBR103 with HDSDR + ExtIO_sddc.dll to program ADC clocks.
Run stream.exe I got the same problem after some time ( 5 minutes in the example )
The bug seems to be in the FX3 device firmware because it happens with 3 different application.
During Summer holidays I experimented about decimation scheme of BreadBoard RF103.
The ExtIO_sddc.dll processes the ADC real signal stream. The sampling rate is 64 MHz. The output is a decimated I&Q complex signal stream at 16 MHz, 8MHz, 4MHz or 2MHz. Filtering and tuning are integrated.
The dll uses CyAPI library to connect BBRF103 hardware via USB3.0. A USBthreadProc thread uses 16 buffers queue to receive data chunk of 65536 samples (short). One buffer’s time duration is about 1 ms at 64 MHz. I configured USBthreadProc to run at high priority to be responsive to hardware timing. The USBthreadProc output buffer is processed by the class RFddc that has an own buffer array of 16 elements. The time of a circular turn of 16 buffers queue allows the digital down conversion algorithm of each chunk to complete on a separate thread. The previously computed output vector is returned while the signal processing of the buffer is started. A priority for these threads below normal seems good enough. Frequency domain signal processing is used. An overlap and add FFT scheme processes the buffer 65536 sample frame and overlap and save scheme glues the buffers together.
The following diagram represents the processing of one buffer frame and it is implemented in every thread of the RFddc pool of 16.
1) It is the input sample array of short. It is a real signal. The frame buffer is a sequence of 65536 samples (it can be seen as a sequence of 64 *1024 slice).
2) The last 1024 slice in the past is copied at the beginning of the array to form a frame of 65 *1024 = 66560 samples. This is the overlap and save scheme.
3) A complex array 66560 samples long is obtained from (2) adding a zero imaginary component.
4) Starting from 0 the array is divided into slices of 768 samples to implement override and add (Overlap and add method) with an overlap of 256 and a fast Fourier transform (FFT) of 1024 sample frame.
5) Every 768 slice is copied into a 1024 one adding a tail of 256 sample zero filled. 85 slice of 1024 complex samples.
6) A FFT forward is applied to the every 1024 slice. 85 slices in frequency domain are computed.
7) For every slide a circular shift of the FFT’s bins is used to implement tuning to the IQ carrier frequency. The resolution is 64000000/1024 = 62500 Hz. This coarse step is good enough for HDSDR tuning that uses its own fine adjustment. A phase adjustment is required depending on the tuning bin position.
9) Decimation in frequency is used. The implemented output lengths are 256,128,64,32 that obtains output rate of 16MHz, 8MHz, 4MHz, 2MHz. It is made just copying the decimated FFT bins chunk near zero frequency.
10) The resulting output is a sequence of decimated FFT ( 256,…) bins. Steps (7) (8) (9) are implemented together in a copy and modify loop.
11) The 85 slices of decimated FFT.
12) The FFT inverse is computed.
13) The time output is computed with overlap and add of the 85 slices. The first 256 samples and the latest 512 are dropped using overlap and save (Overlap save method) of the 64 * decimated FFTN samples frames. The function has an array of 65536 samples input and returns an array of 16.384 samples at 16MHz, 8.192 at 8MHz, 4.096 at 4MHz, 2.048 at 2MHz. A separate thread processes the signal from each one buffer.
CPU use of HDSDR and ExtIO_sddc, V0.95 ADC 64MHz, IQ 16Msps ; 60 s plot
I made some debug measuring the time jitter of USBthreadProc 16 buffer cycle. The theoretical time is 16 * 1.024 ms = 16.384 ms. Here after a plot of the measured duration time - 16.384 ms. The plot shows that the peak jitter is within +/- 3mS.
USBthreadProc 16 buffer circle timing jitter running at 64 MHz in 16MHz sampling output, 60 s plot.
I named this release version 0.95 and I save it in a separate GitHub repository at:
These are exciting times for homemade construction of Software Designed Radio (SDR). Our laptop and desktop have more computing power. Better compilers simplify multi thread programming. Computer interfaces run at higher throughput rate.
I designed the breadboard BBRF103 to learn how to use and to test the following components :
ADC (LTC2217) samples the real data at 16 bit up to 105 Msps.
0-30MHz input, attenuator (0,-10,-20 dB) and LPF transfer antenna signal to the ADC.
Tuner ( R820T2 ) down converts signals in the 30-1800 MHz range to the ADC.
Clock generator ( Si5351A ) outputs the clocks to the ADC and the R820T2.
In other words the idea is to avoid the Digital Down Converter (DDC) Custom or FPGA chip in between ADC and PC. The full HF radio spectrum is processed by the host computer connected via an USB3.0 port.
BBRF103 is placed in series between Antenna and Computer. A modern pc (I5-I7 CPU or higher) equipped with USB 3.0 is required.
The R820T2 chip has been added to look at its performance with a 16 bit ADC and wide bandwidth.
The hardware uses two separate antenna connectors 0-30MHz and 30MHz-1.8GHz
I made the schematic using cut and paste of the main components test circuits.
The HF input (0-30 MHz) is routed to a multiplexer circuit. Some resistors implement a step attenuator with value 0, -10 , -20 dB. The attenuator's output goes to a low pass filter and then to the ADC input via a balancing transformer. The ADC parallel output bus is routed to the FX3 SuperSpeed Explorer Kit using the kit IO connectors. The Cypress kit uses some GPIOs as control of multiplexer and ADC while a I2C bus is used to program the Si5351a clock generator and the R820T2 tuner.
The input multiplexer other than the HF input selects the R820T2 tuner output.
The R820T2 uses an indipendent input (30MHz - 1.8GHz) connector. The Si5351a tuner generates by the tuner reference clock; the first software prototype setup uses a 32 MHz. The software may program different reference frequency to move out of band spur signals.
The Si5351a generates also the ADC clock . The pcb previews an optional backup alternative with a fixed frequency oscillator.
The Si5351a's reference Xtal is 27.000MHz. Another frequency may be used. This is the only frequency reference of all the hardware. The software will be able to compensate the accuracy of this xtal with a correction coefficient.
The clock is coupled to the ADC LTC2217 using a rf balancing transformer.
An extruded aluminum box of 100 * 76 * 35 mm is large enough to accommodate the FX3 SuperSpeed Explorer kit and board PCB.
The size of the PCB is about 100x70 mm. Two 40x2 headers connect the FX3 SuperSpeed Explorer kit.
The PCB board contains the main components on the underside. The ADC has a copper radiator on the top. It taps the aluminum box to dissipate part of the ADC heat.
The two RF input connectors are SMA.
On the upper side there are the power regulator, pin connectors and two jumper cables in coaxial cable for the R820T2 clock and the IF signal.
The final assembly of the prototype shows the FX3 kit at the top of the BBRF103 board.
The prototype has a 5 volt Auxiliary Power Connector that was used during the first tests. It is not necessary because the required current is less than 800mA and can be supplied by the standard USB3.0 connection.
The prototype has been tested with the HDSDR application that i like a lot (THANKS to Mario Taeubel and Alberto di Bene).
I designed an ExtIO_sddc.dll. The name stands for ExtIO software digital down convertion. The dll task is to tune and to downconvert the SDR real samples, generating a IQ complex downsampled stream that is processed by the HDSDR application.
A friend of mine phoned me its appreciation for the performance of the unit and the possibility to use it as high performance receiver. Other than the powerful Spike application Signal Hound provides the ExtIO_BB60.dll for use with HDSDR.
I decided to dig into the BB60c API manual and ExtIO_BB60.dll source code looking for higher sampling rate. A real time signal demodulation in a wider I/Q bandwidth. My ExtIO_BB60c.dll version runs up to 40Msps sampling rate and shows 27 MHz bandwidth. I named it ExtIO_BB60c.dll. It allows the selection of sampling rate, up to 40Msps.
Input sampling rate selection under Bandwidth button
HDSDR + ExtIO_BB60c running in real time at 40Msps.
HDSDR (version 275 or 270) can record the RF spectrum as a filename.wav. The recording at 10Msps is fine. Nevertheless at 20Msps or 40Msps the recording shows some discontinuities every second. Hereafter a 10Msps playback loop video example.
I used a 31 stages long LFSR with 2 taps: [31, 28] in Fibonacci configuration. The generator output bits are computed in 8 bit burst and sent to the SPI serializer at a clock rate that can be selected between 2, 1, 0.5, 0.25, 0.125 Mbps. Some clock phase skewing is caused by the USB routine interrupts but it seems not affecting the resulting randomness. In the following the clock was set at 1 MHz.
The output sequence period is 2^31 -1 clocks = 2.147.483.647 microseconds = 2.147 seconds = 35 minutes
31 bit LFSR fits into a 32 bit integer and output period is long enough to easily cover the latency delay in between the tre RTL-SDR USB receivers.
The uP output signal is as follows:
The signal frequency shape (sinx/x)^2 depends on the rectangular bit shape with clk 1uS that has a spectrum with minimums at 1MHz division.
The measure shown in 3radio project - part 4 are repeated with different receiver frequency. It computes the cross correlation between sequences of 100000 samples.
Center frequency 69 MHz sampling 2.048 Msps
The pseudo randomness of the sequence improves the cross correlation results versus the previous test. Side lobes are low and the time latency between different RTL-SDR is within the 100000 bit analysis span used.
Center frequency 101.800 MHz sampling 2.048 Msps
Center frequency 144.000 MHz sampling 2.048 Msps
This measure shows the presence of a constant pattern that generates the triangular shape on the image on the left while on the right one it causes the minimum value offset.
I think the reason can be the presence of the 28.800 MHz x 5 = 144 MHz harmonic spur that it's synchronous and quite strong.
The following measure shows the results at 142000 MHz where there are lower spurs.
Center frequency 142.000 MHz sampling 2.048 Msps
Center frequency 500.000 MHz sampling 2.048 Msps
The correlation measure at 500 MHz shows that this frequency without a pulse shaping is the limit of the usable range and the peak value is 40 dB lower (100 times) than in VHF tests.
Possibly the use of a shape pulse circuit flattens the spectrum and increases the energy at higher frequency.
Here some test results to evaluate the hardware performance and the use of a pseudo random binary sequence as reference to cross correlate the streams received from the 3radio, a radio composed by multiple RTL-SDR hardware.
The 3radio has been tuned to 69 MHz center frequency and a sampling rate of 2048000 Hz has been chosen. 3 streams of 100000 IQ sample have been recorded using librtlsdr . The real time length is half a second.
The reference signal was a pseudo noise digital stream at 2 MHz shift rate.
The same signal was routed via separated switching diodes to all the RTL-SDR receivers.
Sequences of about 3 ms or 6000 bits have been generated. A delay of some hundred of ms separates the different bursts. The reason was to be able to recognize some sync reference just looking to signals in time.
The previous figure shows the IQ streams in time, a chunk of about 6200 samples at 2048000 sampling is selected.
A script in python was written to compute the cross correlation. Here after the script:
# ik1xpv oscar steila 2016 # complex cross correlation of N files with 8 bit rawIQ data (RTL-SDR)
import math import cmath import matplotlib.pyplot as plt import numpy as np from scipy import signal
signals =  #array of processed signals
# data raw IQ files [howmany required] rawfiles = ["testX1", "testX2", "testX3"]
# The raw, captured IQ data is 8 bit unsigned data. # Each I and Q value varies from 0 to 255. # To get from the unsigned (0 to 255) range we need to subtract 127.5 # from each I and Q value, which results in a new range from -127.5 to +127.5. # The complex data is y = I + jQ and we subtract 127.5 +127.5j
for filename in rawfiles: y = np.fromfile(filename, dtype=np.dtype("u1")) y = y.astype(np.float32).view(np.complex64) y -= (127.5 + 127.5j) signals.append(y)
ncorr = len(signals) chunk_length = len(signals) print(str(ncorr) + " sample vectors of " +str( chunk_length) +" samples length" ) print("filenames:",rawfiles) for i in range(ncorr): sig1 = signals[i] ix = i+1 if ix == ncorr: ix = 0 sig2 = signals[ix] print("cross correlation",i,"<->",ix) ccorr = signal.fftconvolve(sig1, np.conj(sig2[::-1])) mod = np.linalg.norm(sig1)*np.linalg.norm(sig2[::-1]) print("mod", mod) print("ccorr lenth", len(ccorr)) peakat = np.argmax(np.abs(ccorr)) print ("max position:", peakat) print ("ccorr peak value:", cmath.polar(ccorr[peakat])) print ("normalized value:", cmath.polar(ccorr[peakat])/mod,"\n" ) zcorr = ccorr[peakat - 500: peakat + 500]/mod ss = "Correlation "+str(i)+"-"+str(ix) plt.figure("CROSS CORRELATION") plt.subplot(3,1,1+i) plt.text(60000,2*1e7,ss) plt.plot(np.abs(ccorr))
plt.figure("normalized zoom near maximum") plt.subplot(3,1,1+i) plt.xlabel('note: signals are aligned with the max in position 500') plt.text(20,0.1,ss) plt.plot(np.abs(zcorr))
The cross correlation was computed over the whole streams length of 1000000 samples.
The results look quite good nevertheless the reference signal was far from perfect as you can notice from the cross correlation side lobes.
The time differences of the max positions define the time skewing between the streams. This time depends on the USB latency, on the different starting time of the software application trigger. I hope that the hardware clock skewing is solved with the synchronization.
The programmable 2-PLL VCXO clock synthesizer CDCE925 from TI is configured to generate 12 MHz and 16 MHz clocks synchronous to the 28.8 MHz clock reference.
The 3radio prototype has been modified following the scheme:
TI ClockPro(TM) application is used to made the configuration file of CDCE925 while an I2C programmer (an Arduino board) is required to program it.
Other than the 12 MHz and 16 MHz clocks used for the HUB FE1.1s IC and the AT90USB162 uP a 10 MHz synchronous clock is generated for comparison to lab frequency standard.
The 28.8 MHz buffered output goes to a two xtal filter made with the 28.8 MHz xtals de-soldered from the RTL-SDR. This filter is used to obtain the sinusoidal output signal that synchronizes the RTL-SDR dongles.
The FFT analysis shows a 40 dB attenuation of high harmonics.
The CDCE925 has been mounted with dead-bug style and the cable used for the rtl-sdr 28.8MHz is RG174. The cables have the same length, while for 12 MHz and 16 MHz a twisted wire pair has been used.
The 28.8 MHz TCXO and the 28.8 MHz xtal filter are on the top while the cdce925 is on the bottom side of the PCB. The black cables feed the clock to the RTL-SDR dongles. The grey twin wires on the left are the 12 and 16 MHz clocks.
The software uses rtl-sdr library. It runs 3 instances using synchronous transfer. Each stream is recorded in a file as raw bytes. A first graphical analysis and comparison is made using Audacity application.
The application programs all the units to the same frequency. The central frequency is 60.0 MHz because the energy of Pseudo Random Noise Generator (PRNG) sequence is higher at low frequency. The 3radio PRNG prototype has not jet a pulse sharpening circuit.
The PRNG has been programmed to generate at pseudo-random time intervals a sequence of 64 bits at 1Mbps with a good auto-correlation peak. Nevertheless the first measure has been made without any correlation processing, just looking at signal in time with Audacity app.
The picture shows the records made with a sampling rate of 2048 ksps and the gain set to 10dB. All the units are feed by the same PRNG signal. The signals are down-converted and recorded as complex base-band signal I&Q, here shown as stereo audio signals. The time scale is in 10 ms units as Audacity does not accept 2048 kHz sampling and 20.48 kHz is selected instead. The time span is about 500 ms.
The 3 streams are correlated and shown different latency time. I think latency is due to the different recording starting time and serialization over the USB link other than the pll phasing of RTL2832 and R820T.
Lucky the sampling synchronization is kept constant during the measure. So an head synchronization could be maintained for a long time.
Manually phasing the signals and zooming into the 64 bit sequence shows the strong correlation in between the 3 I&Q streams.
A phase rotation in the signals is expected as the PRNG signal is generated by a microprocessor running at 16.0 MHz with a xtal not synchronous to the 28.8MHz clock.
Note: an hardware improvement could be made synchronizing the 16.0 MHz clock of PRNG and the 12.0 MHz clock of HUB with the advantage of decreasing the eterodine signals.
This pages describe my own project of a SDR coherent receiver named 3radio
The first goal is a setup for coherence measure without sophisticate instruments.
Block diagram rev 1.0
It is a compact device that uses a single USB cable to acquire 3 SDR sample streams.
Thermal cooling is important to reach reliable performance.
The unit is housed into an aluminum box with the rtl-sdr screwed to the box wall.
Temperature range from 25°C to 85°C
The original MCX connector, the IR receiver and the led have been removed. Please keep the solder dots as flat as possible on the solder side.
The rtl-sdr PCB has a 2.0 mm hole that can be used to fix the unit near the led position. A second 2.0 mm diameter hole is drilled in the position indicated in the picture. Two 2.0 mm screws will rest the board against the aluminum wall. An electrical insulated thermal pad is placed in between the board and the aluminum. 90° SMA Female connectors has been used in the prototype.
Preliminary test wiring with a xtal oscillator feeding the other units.
As the TCXO 28.8MHz is not jet arrived in the mail, one of the original xtal oscillators has been used to drive the other two ones using a 14 pF capacitors (2*6.8pF in parallel).
The USB connectors has been replaced by wires to place the boards against the aluminum near the HUB PCB.
The red wire that goes to the antenna diode is carrying the pseudo random noise PRNG signal to the antenna inputs via a BAV99 diode gate.
The HUB is a FE1.1s chip while the PRNG is a AT90USB162 wired to the 4th port of the HUB.
The plan is to use the PRNG sequence to synchronize the received streams during an initial calibration phase or every time the USB samples streams are stopped.
At the beginning the generator stream is used to measure some coherence figure...