The programmable 2-PLL VCXO clock synthesizer CDCE925 from TI is configured to generate 12 MHz and 16 MHz clocks synchronous to the 28.8 MHz clock reference.
The 3radio prototype has been modified following the scheme:
TI ClockPro(TM) application is used to made the configuration file of CDCE925 while an I2C programmer (an Arduino board) is required to program it.
Other than the 12 MHz and 16 MHz clocks used for the HUB FE1.1s IC and the AT90USB162 uP a 10 MHz synchronous clock is generated for comparison to lab frequency standard.
The 28.8 MHz buffered output goes to a two xtal filter made with the 28.8 MHz xtals de-soldered from the RTL-SDR. This filter is used to obtain the sinusoidal output signal that synchronizes the RTL-SDR dongles.
The FFT analysis shows a 40 dB attenuation of high harmonics.
The CDCE925 has been mounted with dead-bug style and the cable used for the rtl-sdr 28.8MHz is RG174. The cables have the same length, while for 12 MHz and 16 MHz a twisted wire pair has been used.
The 28.8 MHz TCXO and the 28.8 MHz xtal filter are on the top while the cdce925 is on the bottom side of the PCB. The black cables feed the clock to the RTL-SDR dongles. The grey twin wires on the left are the 12 and 16 MHz clocks.