These are exciting times for homemade construction of Software Designed Radio (SDR).  Our laptop and desktop have more computing power. Better compilers simplify multi thread programming. Computer interfaces run at higher throughput rate. 

I designed the breadboard BBRF103 to learn how to use and to test the following components :

  • FX3 SuperSpeed Explorer Kit USB3.0 transfers the ADC sample stream to the PC.
  • ADC (LTC2217) samples the real data at 16 bit up to 105 Msps.
  • 0-30MHz input, attenuator (0,-10,-20 dB) and LPF transfer antenna signal to the ADC.
  • Tuner ( R820T2 ) down converts signals in the 30-1800 MHz range to the ADC.
  • Clock generator ( Si5351A ) outputs the clocks to the ADC and the R820T2.



In other words the idea is to avoid the Digital Down Converter (DDC)  Custom or FPGA chip in between ADC and PC. The full HF radio spectrum is processed by the host computer connected via an USB3.0 port.

BBRF103 is placed in series between Antenna and Computer. A modern pc (I5-I7 CPU or higher) equipped with USB 3.0 is required.

The R820T2 chip has been added to look at its performance with a 16 bit ADC and wide bandwidth. 



The hardware uses two separate antenna connectors  0-30MHz  and  30MHz-1.8GHz

I made the schematic using cut and paste of the main components test circuits. 

The HF input (0-30 MHz) is routed to a multiplexer circuit. Some resistors  implement a step attenuator with value 0, -10 , -20 dB. The attenuator's output goes to a low pass filter and then to the ADC input via a balancing transformer. The ADC parallel output bus is routed to the FX3 SuperSpeed Explorer Kit using the kit IO connectors. The Cypress kit uses some GPIOs as control of multiplexer and ADC while a I2C bus is used to program the Si5351a clock generator and the R820T2 tuner.

The input multiplexer other than the HF input selects the R820T2 tuner output. 

The R820T2 uses an indipendent input (30MHz - 1.8GHz) connector.  The Si5351a tuner generates by the tuner reference clock; the first software prototype setup uses a 32 MHz. The software may program different reference frequency to move out of band spur signals.

The Si5351a generates also the ADC clock .  The pcb previews an optional backup alternative with a fixed frequency oscillator. 

The Si5351a's reference Xtal is 27.000MHz. Another frequency may be used. This is the only frequency reference of all the hardware. The software will be able to compensate the accuracy of this xtal with a correction coefficient. 

The clock is coupled to the ADC LTC2217 using a rf balancing transformer.  



An extruded aluminum box of 100 * 76 * 35 mm is large enough to accommodate the FX3 SuperSpeed Explorer kit and board PCB.

The size of the PCB is about 100x70 mm. Two 40x2 headers connect the FX3 SuperSpeed Explorer kit.


The PCB board contains the main components on the underside. The ADC has a copper radiator on the top. It taps the aluminum box to dissipate part of the ADC heat.

The two RF input connectors are SMA.


On the upper side there are the power regulator, pin connectors and two jumper cables in coaxial cable for the R820T2 clock and the IF signal.


The final assembly of the prototype shows the FX3 kit at the top of the BBRF103 board. 


The prototype has a 5 volt Auxiliary Power Connector that was used during the first tests.  It is not necessary because the required current is less than 800mA and can be supplied by the standard USB3.0 connection.

The hardware scheme and pcb layout at .


The FX3 firmware is a modification of Cypress streaming examples. Some Vendor commands have been added to control I2C bus and to control GPIO e PWM output.

SDK comes with the Cypress Eclipse development enviroment. It's a nice exercise to learn how to use FX3.

BBRF103 uses the Cypress USB driver that comes with FX3 Kit.

The firmware source repository is



The prototype has been tested with the HDSDR application that i like a lot (THANKS to Mario Taeubel and Alberto di Bene).

I designed an ExtIO_sddc.dll. The name stands for ExtIO software digital down convertion. The dll task is to tune and to downconvert the SDR real samples, generating a IQ complex downsampled stream that is processed by the HDSDR application.

The software source repository is .

Here a video of BBRF103 prototype with a 1 meter wire antenna receiving local FM band in Turin. The PC used is a I5-3350P CPU @3.10GHz desktop


 I prepared a portable setup for summer holidays using a Laptop  i7-7500U CPU @2.70 GHZ  2.90 GHz


 To be continued.