It uses the same USB3 Cypress Explorer Kit Board while the ADC is a LTC2206.
Reginald Eisenblatt, gave a presentation on the BooyaSDR ( January 23, 2017, at Linaspace see http://www.amrad.org/ ).
Some video at https://www.youtube.com/watch?v=uF6y0ETTJFA , notice the Waterfall with multiple rows!
The BooyaSDR application is very clever. It uses gcc compiler with pthreads and fftw library. The FX3 firmware is loaded at run time using the Cypress download protocol.
I decided to use the same software environment and compiler to test a version of ExtIO_sddc.dll for BBRF103 with pthreads lib.
To install CodeBlocks 12.11 IDE , https://sourceforge.net/projects/codeblocks/files/Binaries/12.11/Windows/ download codeblocks-12.11mingw-setup.exe -> Default installer WITH compiler (MinGW).
ExtIO_sddc.dll ver 0.96 project links to the following libraries:
copy Pre-built.2 directory contens into /lib/pthreads/.
a gcc compiled version of CyAPI.cpp.
library source can be downloaded at http://www.cypress.com/file/289981/download
(see License) .
The directories structure I used is:
ExtIO_sddc \ readme.txt ,
ExtIO_sddc \BBRF103_SE FX3 firmware,
ExtIO_sddc \source\ sources, ExtIO_sddc.cbp,
ExtIO_sddc \Lib\fftw fftw library,
ExtIO_sddc \Lib\pthreads pthreads library ,
ExtIO_sddc \Lib\CyAPI_gcc CyAPI gcc library ,
ExtIO_sddc \bin\debug debug ExtIO_sddc.dll, HDSDR ,
ExtIO_sddc \bin\release release ExtIO_sddc.dll, HDSDR.
The bin\release and \bin\debug directories contain:
ExtIO_sddc.dll release or debug
BBRF103_SE.img BBRF103 firmware image
Sources repository :
An archive file of project with compiled binaries can be download at
The BBR103 has been updated to version 0.2 with the following patch.
- RAND patch: a wire has been added to control the RAND pin of ADC using GPIO20 of FX3.
This option allows the control and test of RAND feature of ADC (see pg 14, 24 of http://cds.linear.com/docs/en/datasheet/2217f.pdf).
The wire connects RAND (U3-pin 63, R7,R9) to GPIO20 ( BGA K7 = PIN25 J6 FX3 SS kit).
The Firmware source can be found into the archive file of project under \Firmware directory
The 0.96 version is still a preliminary release with some bugs. It operates in HF mode only.
Problems remain in use of R820T2 tuner, and a post on this argument will follow.
The digital signal processing frontend uses a the Halfcomplex-format DFT (http://www.fftw.org/fftw3_doc/The-Halfcomplex_002dformat-DFT.html).
The FFT output is sent to HDSDR with a selectable rate of 32 Msps or a decimated one at 16, 8, 4, 2 Msps.
Filtering and tuning is made using overlap and add with frame of 1024 as 768 +256 samples. The filter time responses are 257 sample long.
When 32Msps is used the local oscillator of HDSDR is fixed to 16 MHz at centre of spectrum and the fine tuning of HDSDR allows reception from 500 kHz to 31500 kHz, while with lower sample rates the local oscillator can be tuned with 125 kHz step while the fine tuning is made by HDSDR.
At this development stage ExtIO_sddc.dll has a GUI dialog with 4 tabs :
- Status - reports ADC rate and I&Q rate.
- BBRF103 - buttons :
LW-MW this is used to modify the FFT output filtering to receive the low frequency band.
HF - standard HF setup .
VHF - enables R820T2 ( it is disabled, to enable undefine _NO_TUNER_ in config.h and recompile)
DITH - enables the ADC dither.
RAND - enables the ADC randomize.
TRACE - enabled in debug mode to trace some signals to log files.
RF ADC stream: it requires BB103, ADC input ,default,
RF virtual tone: it requires BB103, virtual tone,
RF virtual sweep: it requires BB103, virtual sweep,
IF virtual tone: NO hardware required, virtual tone ,
IF virtual sweep: NO hardware required, virtual sweep,
Hereafter a video recorded with a random wire antenna 5mt long on the balcony (in the city).