In the construction of BBRF103 the evaluation kit of Cypress for the FX3 is used as it is and the ADC printed circuit board is realized with 2 layers as a compromise to reduce the cost of realization.

I try to evaluate now with homemade measurements how close the performance is and how good it is.

Let's start with a few readings from the technical data sheet of the LTC2217 ( )

"(pag 1) ...The LTC2217 includes 81.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR)

(pag 24) … Digital Output Randomizer
Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling, or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude.
The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output Randomizer function is active when the RAND pin is high.


(pag 25)... Internal Dither
The LTC2217 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels.
As shown in Figure 15, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in typically less than 0.5dB elevation in the noise floor of the ADC as compared to the noise floor with dither off, when a suitable input termination is provided (see Demo Board schematic DC996B).



I made a sinusoidal generator using an old 10MHz TCXO followed by a ladder quartz filter made with cheap 10MHz quartz.

I calibrated the TCXO at 9.9981 MHz to pass through the quartz filter.
Before the filter, an SBF5089Z amplifier allows to obtain after the filter a level of +2dBm on 50 Ohm.
Finally, a series of resistive attenuators allows you to adjust the output level.
The aim is to obtain a generator with good dynamics and low noise. The result has 2nd and 3rd harmonic level at -50dB.

Here are a few measures

BBRF103 HF antenna is connected to the attenuator output.
BBRF103 control panel allows to activate dither and randomize.


Hereafter the level is -1dBFS, DITH and RAND are active.


High resolution image link


Hereafter the same -1dBFS level, DITH and RAND are OFF


High resolution image link

With strong and stationary signals the interference of the data bus is evident and the use of dither and randomize is effective.
Referring to the ADC datasheet with reference to these approximate measurements, it seems to me that the current layout of the 2-layer PCB and the adc databus, which also continues in the evaluation PCB of the FX3, worsen the spurious performance by 10-15 dB compared to the optimal layout of the PCB.

It would be possible to realize a single multilayer PCB including FX3 and ADC with better performances following the datasheet's layout indications.